AD80066 Datasheet, PDF (19/20 Pages) Analog Devices – Complete 16-Bit CCD/CIS Signal Processor

AD80066
APPLICATIONS INFORMATION
CIRCUIT AND LAYOUT RECOMMENDATIONS
Figure 23 shows the recommended circuit configuration for
4-channel CDS mode operation. The recommended input
coupling capacitor value is 0.1 μF (see the Analog Inputs—CDS
Mode section). A single ground plane is recommended for the
AD80066. A separate power supply can be used for DRVDD,
the digital driver supply, but this supply pin should still be
decoupled to the same ground plane as the rest of the AD80066.
The loading of the digital outputs should be minimized, either
by using short traces to the digital ASIC or by using external
digital buffers. To minimize the effect of digital transients
during major output code transitions, the falling edge of
CDSCLK2 should occur coincident with or before the rising
edge of ADCCLK (see Figure 3 through Figure 8 for timing).
All 0.1 μF decoupling capacitors should be located as close as
possible to the AD80066 pins. When operating in 1-channel
mode, the unused analog inputs should be grounded.
Figure 24 shows the recommended circuit configuration for
4-channel SHA mode. All of the previously explained consid-
erations also apply to this configuration, except that the analog
input signals are directly connected to the AD80066 without the
use of coupling capacitors. Before connecting the signals, the
analog input signals must be dc-biased between 0 V and 1.5 V
or 3 V (see the Analog Inputs—SHA Mode section).
CLOCK
INPUTS
3.3V
0.1µF
DATA
INPUTS
5V
0.1µF
AVDD
1
28
CDSCLK1
2
27
CDSCLK2
3
26
ADCCLK
4
25
DRVDD
5
24
DRVSS
(MSB) D7
D6
6
23
AD80066
7 _{TOP VIEW} 22
8 ^{(Not to Scale)} 21
D5
9
20
D4
10
19
D3
11
18
D2
12
17
D1
13
16
(LSB) D0
14
15
AVSS
VINA
OFFSET
VINB
CML
VINC
CAPT
CAPB
VIND
AVSS
AVDD
SLOAD
SCLK
SDATA
0.1µF
0.1µF
A INPUT
B INPUT
0.1µF
0.1µF
0.1µF
1.0µF
0.1µF
0.1µF
10µF
0.1µF
0.1µF
C INPUT
D INPUT
0.1µF
5V
SERIAL
INTERFACE
Figure 23. Recommended Circuit Configuration, 4-Channel CDS Mode
5V
0.1µF
A INPUT
CLOCK
INPUTS
2
3.3V
0.1µF
AVDD
1
AVSS
28
CDSCLK1
2
VINA
27
CDSCLK2
3
OFFSET
26
ADCCLK
4
VINB
25
DRVDD
5
CML
24
DRVSS
6
VINC
23
(MSB) D7
7
AD80066
CAPT
22
D6
TOP VIEW
CAPB
8 _{(Not to Scale)} 21
D5
VIND
9
20
D4
10
AVSS
19
D3
11
AVDD
18
D2
12
SLOAD
17
D1
13
SCLK
16
(LSB) D0
14
SDATA
15
B INPUT
0.1µF
0.1µF
0.1µF 10µF
0.1µF
0.1µF
5V
C INPUT
D INPUT
DATA
INPUTS
SERIAL
INTERFACE
Figure 24. Recommended Circuit Configuration, 4-Channel SHA Mode (Analog Inputs Sampled with Respect to Ground)
Rev. A | Page 19 of 20