AD80066 Datasheet, PDF (1/20 Pages) Analog Devices – Complete 16-Bit CCD/CIS Signal Processor

Complete 16-Bit
CCD/CIS Signal Processor
AD80066
FEATURES
GENERAL DESCRIPTION
16-bit, 24 MSPS analog-to-digital converter (ADC)
The AD80066 is a complete analog signal processor for imaging
4-channel operation up to 24 MHz (6 MHz/channel)
applications. It features a 4-channel architecture designed to sample
3-channel operation up to 24 MHz (8 MHz/channel)
and condition the outputs of linear charged coupled device (CCD)
Selectable input range: 3 V or 1.5 V peak-to-peak
or contact image sensor (CIS) arrays. Each channel consists of
Input clamp circuitry
an input clamp, correlated double sampler (CDS), offset digital-
Correlated double sampling
to-analog converter (DAC), and programmable gain amplifier
1×~6× programmable gain
±300 mV programmable offset
Internal voltage reference
Multiplexed byte-wide output
Optional single-byte output mode
3-wire serial digital interface
3 V/5 V digital I/O compatibility
Power dissipation: 490 mW at 24 MHz operation
Reduced power mode and sleep mode available
28-lead SSOP package
APPLICATIONS
(PGA), multiplexed to a high performance 16-bit ADC. For
maximum flexibility, the AD80066 can be configured as a
4-channel, 3-channel, 2-channel, or 1-channel device.
The CDS amplifiers can be disabled for use with sensors that
do not require CDS, such as CIS and CMOS sensors.
The 16-bit digital output is multiplexed into an 8-bit output word,
which is accessed using two read cycles. There is an optional
single-byte output mode. The internal registers are programmed
through a 3-wire serial interface and enable adjustment of the
gain, offset, and operating mode. The AD80066 operates from a
5 V power supply, typically consumes 490 mW of power, and is
Flatbed document scanners
packaged in a 28-lead SSOP.
Film scanners
Digital color copiers
Multifunction peripherals
FUNCTIONAL BLOCK DIAGRAM
AVDD AVSS
CML
AVDD AVSS
CAPT CAPB
DRVDD DRVSS
VINA
CDS
9-BIT
DAC
PGA
BAND GAP
REFERENCE
AD80066
VINB
VINC
VIND
OFFSET
CDS
9-BIT
DAC
CDS
9-BIT
DAC
CDS
9-BIT
DAC
INPUT
CLAMP
BIAS
PGA
PGA
PGA
9
CDSCLK1 CDSCLK2
4:1
MUX
16-BIT
16
16:8 ⁸
ADC
MUX
CONFIGURATION
REGISTER
MUX
REGISTER
6
CH. A
CH. B
CH. C
CH. D
CH. A
CH. B
CH. C
CH. D
GAIN
REGISTERS
OFFSET
REGISTERS
Figure 1.
ADCCLK
DIGITAL
CONTROL
INTERFACE
DOUT
(D[0:7])
SCLK
SLOAD
SDATA
Rev. A
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