AD1848K Datasheet, PDF (19/28 Pages) Analog Devices – Parallel-Port 16-Bit SoundPort Stereo Codec

AD1848K
Test and Initialization Register (IXA3:0 = 11)
IXA3:0
11
Data 7
COR
Data 6
PUR
Data 5
ACI
Data 4
DRS
Data 3
ORR1
Data 2
ORR0
Data 1
ORL1
Data 0
ORL0
ORL1:0 Overrange Left Detect. These bits indicate the overrange on the left input channel. This bit changes on a sample-by
sample basis. This bit is read only.
0 Less than –1 dB underrange
1 Between –1 dB and 0 dB underrange
2 Between 0 dB and +1 dB overrange
3 Greater than +1 dB overrange
ORR1:0 Overrange Right Detect. These bits indicate the overrange on the right input channel. This bit changes on a sample-by
sample basis. This bit is read only.
0 Less than –1 dB underrange
1 Between –1 dB and 0 dB underrange
2 Between 0 dB and +1 dB overrange
3 Greater than +1 dB overrange
DRS
Data Request Status. This bit indicates the current status of the PDRQ and CDRQ pins of the AD1848K.
0 CDRQ and PDRQ are presently inactive (LO)
1 CDRQ or PDRQ are presently active (HI)
ACI
Autocalibrate-In-Progress. This bit indicates the state of autocalibration or a recent exit from Mode Change Enable
(MCE). This bit is read only.
0 Autocalibration is not in progress
1 Autocalibration is in progress or MCE was exited within approximately the last 128 sample periods
PUR
Playback Underrun. This bit is set when playback data has not arrived from the host in time to be played. As a result, a
midscale value will be sent to the DACs. This bit changes on a sample by sample basis.
COR
Capture Overrun. This bit is set when the capture data has not been read by the host before the next sample arrives. The
sample being read will not be overwritten by the new sample. The new sample will be ignored. This bit changes on a
sample by sample basis.
The occurrence of a PUR and/or COR is designated in the Status Register’s Sample Overrun/Underrun (SOUR) bit. The SOUR bit
is the logical OR of the COR and PUR bits. This enables a polling host CPU to detect an overrun/underrun condition while checking
other status bits.
This register’s initial state after reset is “0000 0000.”
Miscellaneous Control Register (IXA3:0 = 12)
IXA3:0
12
Data 7
res
Data 6
res
Data 5
res
Data 4
res
Data 3
ID3
Data 2
ID2
Data 1
ID1
Data 0
ID0
res
Reserved for future expansion. The bits are read only. Do not write to these bits.
ID3:0
AD1848K Revision ID. These four bits define the revision level of the AD1848K. Revisions increment by one LSB. The
K-Grade revision is ID = “1010.” These bits are read only.
This register’s initial state after reset is “xxxx RRRR” where RRRR = Revision ID of the silicon in use.
REV. 0
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