AD1848K Datasheet, PDF (17/28 Pages) Analog Devices – Parallel-Port 16-Bit SoundPort Stereo Codec

AD1848K
Clock and Data Format Register (IXA3:0 = 8)
IXA3:0
8
Data 7
res
Data 6
FMT
Data 5
L/C
Data 4
S/M
Data 3
CFS2
Data 2
CFS1
Data 1
CFS0
Data 0
CSS
The contents of the Clock and Data Format Register cannot be changed except when the AD1848K is in Mode Change Enable (MCE) state.
Write attempts to this register when the AD1848K is not in the MCE state will not be successful.
CSS
Clock Source Select. This bit selects the crystal clock source which will be used for the audio sample rate.
0 XTAL1 (24.576 MHz)
1 XTAL2 (16.9344 MHz)
CFS2:0 Clock Frequency Divide Select. These bits select the audio sample rate frequency. The actual audio sample rate depends
on which crystal clock source is selected and the frequency of that source.
Divide
XTAL1
XTAL2
CFS
Factor
24.576 MHz
16.9344 MHz
0
3072
8.0 kHz
5.5125 kHz
1
1536
16.0 kHz
11.025 kHz
2
896
27.42857 kHz 18.9 kHz
3
768
32.0 kHz
22.05 kHz
4
448
Not Supported 37.8 kHz
5
384
Not Supported 44.1 kHz
6
512
48.0 kHz
33.075 kHz
7
2560
9.6 kHz
6.615 kHz
Note that the AD1848K’s internal oscillators can be overdriven by external clock sources at the crystal input pins. If an external
clock source is applied, it will be divided down by the selected Divide Factor. It need not be at the recommended crystal frequencies.
S/M
Stereo/Mono Select. This bit determines how the audio data streams are formatted. Selecting stereo will result with alter-
nating samples representing left and right audio channels. Mono playback plays the same audio sample on both chan-
nels. Mono capture only captures data from the left audio channel.
0 Mono
1 Stereo
L/C
Linear/Companded Select. This bit selects between a linear digital representation of the audio signal or a nonlinear,
companded format for all input and output data. The type of linear PCM or the type of companded format is defined by
the FMT bits.
0 Linear PCM
1 Companded
FMT
Format Select. This bit defines the format for all digital audio input and outputs based on the state of the L/C bit.
Linear PCM (L/C = 0)
Companded (L/C = 1)
0
8-bit Unsigned PCM
8-bit µ-law Companded
1
16-bit Twos-Complement PCM
8-bit A-law Companded
res
Reserved for future expansion. Always write a zero to this bit.
This register’s initial state after reset is “x000 0000.”
REV. 0
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