AD9958_08 Datasheet, PDF (18/44 Pages) Analog Devices – 2-Channel, 500 MSPS DDS with 10-Bit DACs

AD9958
THEORY OF OPERATION
DDS CORE
The AD9958 has two DDS cores, each consisting of a 32-bit
phase accumulator and phase-to-amplitude converter. Together,
these digital blocks generate a digital sine wave when the phase
accumulator is clocked and the phase increment value (frequency
tuning word) is greater than 0. The phase-to-amplitude converter
simultaneously translates phase information to amplitude
information by a cos(θ) operation.
The output frequency (fOUT) of each DDS channel is a function
of the rollover rate of each phase accumulator. The exact
relationship is given in the following equation:
f_OUT
=
(FTW)( f_S )
2³²
where:
fS is the system clock rate.
FTW is the frequency tuning word and is 0 ≤ FTW ≤ 2³¹.
2³² represents the phase accumulator capacity.
Because both channels share a common system clock, they are
inherently synchronized.
The DDS core architecture also supports the capability to phase
offset the output signal, which is performed by the channel
phase offset word (CPOW). The CPOW is a 14-bit register that
stores a phase offset value. This value is added to the output of
the phase accumulator to offset the current phase of the output
signal. Each channel has its own phase offset word register. This
feature can be used for placing all channels in a known phase
relationship relative to one another. The exact value of phase
offset is given by the following equation:
Φ
=
⎜⎝⎛
POW
2¹⁴
⎟⎠⎞
×
360°
DIGITAL-TO-ANALOG CONVERTER
The AD9958 incorporates four 10-bit current output DACs.
The DAC converts a digital code (amplitude) into a discrete
analog quantity. The DAC current outputs can be modeled as a
current source with high output impedance (typically 100 kΩ).
Unlike many DACs, these current outputs require termination
into AVDD via a resistor or a center-tapped transformer for
expected current flow.
Each DAC has complementary outputs that provide a combined
full-scale output current (IOUT + I_OUT). The outputs always sink
current, and their sum equals the full-scale current at any point
in time. The full-scale current is controlled by means of an
external resistor (RSET) and the scalable DAC current control
bits discussed in the Modes of Operation section. The resistor,
RSET, is connected between the DAC_RSET pin and analog
ground (AGND). The full-scale current is inversely proportional
to the resistor value as follows:
R_SET
=
18.91
I_OUT (max)
The maximum full-scale output current of the combined DAC
outputs is 15 mA, but limiting the output to 10 mA provides
optimal spurious-free dynamic range (SFDR) performance.
The DAC output voltage compliance range is AVDD + 0.5 V to
AVDD − 0.5 V. Voltages developed beyond this range may cause
excessive harmonic distortion. Proper attention should be paid
to the load termination to keep the output voltage within its
compliance range. Exceeding this range could potentially dam-
age the DAC output circuitry.
LPF
CHx_IOUT _1:1
DAC
AVDD
50Ω
CHx_IOUT
Figure 32. Typical DAC Output Termination Configuration
Rev. A | Page 18 of 44