AD9958_08 Datasheet, PDF (13/44 Pages) Analog Devices – 2-Channel, 500 MSPS DDS with 10-Bit DACs

–100
–110
75.1MHz
–120
–130
–140
100.3MHz
–150
40.1MHz
–160
–170
10
15.1MHz
100
1k
10k
100k
1M
10M
FREQUENCY OFFSET (Hz)
Figure 16. Residual Phase Noise (SSB) with fOUT = 15.1 MHz, 40.1MHz,
75.1 MHz, 100.3 MHz; fCLK = 500 MHz with REFCLK Multiplier Bypassed
–70
–80
–90
–100
–110
–120
100.3MHz
75.1MHz
–130
–140
–150
–160
40.1MHz
15.1MHz
–170
10
100
1k
10k
100k
1M
10M
FREQUENCY OFFSET (Hz)
Figure 17. Residual Phase Noise (SSB) with fOUT = 15.1 MHz, 40.1MHz,
75.1 MHz, 100.3 MHz; fCLK = 500 MHz with REFCLK Multiplier = 5×
–70
–80
–90
–100
100.3MHz
–110
75.1MHz
–120
–130
–140
–150
40.1MHz
15.1MHz
–160
–170
10
100
1k
10k
100k
1M
10M
FREQUENCY OFFSET (Hz)
Figure 18. Residual Phase Noise (SSB) with fOUT = 15.1 MHz, 40.1MHz,
75.1 MHz,100.3 MHz; fCLK = 500 MHz with REFCLK Multiplier = 20×
AD9958
–60
–65
–70
SINGLE DAC POWER PLANE
–75
–80
–85
25.3
SEPARATED DAC POWER PLANES
50.3 75.3 100.3 125.3 150.3 175.3 200.3
FREQUENCY OF COUPLING SPUR (MHz)
Figure 19. Channel Isolation at 500 MSPS Operation; Conditions are Channel
of Interest Fixed at 110.3 MHz, the Other Channels Are Frequency Swept
600
500
400
2 CHANNELS ON
300
1 CHANNEL ON
200
100
0
500 450 400 350 300 250 200 150 100 50
REFERENCE CLOCK FREQUENCY (MHz)
Figure 20. Power Dissipation vs. Reference Clock Frequency vs. Channel(s)
Power On/Off
–45
–50
SFDR AVERAGED
–55
–60
–65
–70
–75
1.1
15.1
40.1
75.1
100.3 200.3
f_OUT (MHz)
Figure 21. Averaged Channel SFDR vs. fOUT
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