ADXL343 Datasheet, PDF (17/36 Pages) Analog Devices – 3-Axis, ±2 g/±4 g/±8 g/±16 g

Preliminary Technical Data
ADXL343
Table 12. I²C Timing (T_A = 25°C, V_S = 2.5 V, V_{DD I/O} = 1.8 V)
Limit^{1, 2}
Parameter
Min
Max
Unit
f_SCL
t₁
t₂
t₃
t₄
t₅
t ^{3, 4, 5, 6}
6
t₇
t₈
t₉
t₁₀
400
kHz
2.5
µs
0.6
µs
1.3
µs
0.6
µs
100
ns
0
0.9
µs
0.6
µs
0.6
µs
1.3
µs
300
ns
0
ns
t₁₁
300
ns
250
ns
C_b
400
pF
Description
SCL clock frequency
SCL cycle time
t_HIGH, SCL high time
t_LOW, SCL low time
t_{HD, STA}, start/repeated start condition hold time
t_{SU, DAT}, data setup time
t_{HD, DAT}, data hold time
t_{SU, STA}, setup time for repeated start
t_{SU, STO}, stop condition setup time
t_BUF, bus-free time between a stop condition and a start condition
t_R, rise time of both SCL and SDA when receiving
t_R, rise time of both SCL and SDA when receiving or transmitting
t_F, fall time of SDA when receiving
t_F, fall time of both SCL and SDA when transmitting
Capacitive load for each bus line
1 _{Limits based on characterization results, with fSCL = 400 kHz and a 3 mA sink current; not production tested.}
2 _{All values referred to the VIH and the VIL levels given in Table 11.}
3 _{t6 is the data hold time that is measured from the falling edge of SCL. It applies to data in transmission and acknowledge.}
4 _{A transmitting device must internally provide an output hold time of at least 300 ns for the SDA signal (with respect to VIH(min) of the SCL signal) to bridge the}
undefined region of the falling edge of SCL.
5 _{The maximum t6 value must be met only if the device does not stretch the low period (t3) of the SCL signal.}
6 _{The maximum value for t6 is a function of the clock low time (t3), the clock rise time (t10), and the minimum data setup time (t5(min)). This value is calculated as}
t_6(max) = t₃ − t₁₀ − t_5(min).
SDA
t₉
t₃
t₁₀
t₁₁
t₄
SCL
t₄
START
CONDITION
t₆
t₂
t₅
t₇
t₁
REPEATED
START
CONDITION
Figure 32. I²C Timing Diagram
t₈
STOP
CONDITION
Rev. PrA | Page 17 of 36