ADSP-BF524_15 Datasheet, PDF (17/88 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
specified by the crystal manufacturer. The user should verify the
customized values based on careful investigations on multiple
devices over temperature range.
CLKOUT
CLKBUF
BLACKFIN
TO PLL CIRCUITRY
EN
560 ⍀
EN
CLKIN
330 ⍀*
XTAL
FOR OVERTONE
OPERATION ONLY:
18 pF *
18 pF *
NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING
ON THE CRYSTAL AND LAYOUT. PLEASE ANALYZE CAREFULLY. FOR
FREQUENCIES ABOVE 33 MHz, THE SUGGESTED CAPACITOR VALUE
OF 18 pF SHOULD BE TREATED AS A MAXIMUM, AND THE SUGGESTED
RESISTOR VALUE SHOULD BE REDUCED TO 0 ⍀.
Figure 6. External Crystal Connections
A third-overtone crystal can be used for frequencies above
25 MHz. The circuit is then modified to ensure crystal operation
only at the third overtone by adding a tuned inductor circuit as
shown in Figure 6. A design procedure for third-overtone oper-
ation is discussed in detail in application note (EE-168) Using
Third Overtone Crystals with the ADSP-218x DSP on the Analog
Devices website (www.analog.com)—use site search on
“EE-168.”
The CLKBUF pin is an output pin, which is a buffered version
of the input clock. This pin is particularly useful in Ethernet
applications to limit the number of required clock sources in the
system. In this type of application, a single 25 MHz or 50 MHz
crystal may be applied directly to the processor. The 25 MHz or
50 MHz output of CLKBUF can then be connected to an exter-
nal Ethernet MII or RMII PHY device. If, instead of a crystal, an
external oscillator is used at CLKIN, CLKBUF will not have the
40/60 duty cycle required by some devices. The CLKBUF output
is active by default and can be disabled for power savings rea-
sons using the VR_CTL register.
The Blackfin core runs at a different clock rate than the on-chip
peripherals. As shown in Figure 7, the core clock (CCLK) and
system peripheral clock (SCLK) are derived from the input
clock (CLKIN) signal. An on-chip PLL is capable of multiplying
the CLKIN signal by a programmable multiplication factor
(bounded by specified minimum and maximum VCO frequen-
cies). The default multiplier can be modified by a software
instruction sequence. This sequence is managed by the
bfrom_SysControl() function in the on-chip ROM.
On-the-fly CCLK and SCLK frequency changes can be applied
by using the bfrom_SysControl() function in the on-chip ROM.
The maximum allowed CCLK and SCLK rates depend on the
applied voltages V_DDINT, V_DDEXT, and V_DDMEM; the VCO is always
permitted to run up to the frequency specified by the part’s
maximum instruction rate. The CLKOUT pin reflects the SCLK
frequency to the off-chip world. It is part of the SDRAM inter-
face, but it functions as a reference signal in other timing
specifications as well. While active by default, it can be disabled
using the EBIU_SDGCTL and EBIU_AMGCTL registers.
“FINE” ADJUSTMENT
REQUIRES PLL SEQUENCING
“COARSE” ADJUSTMENT
ON-THE-FLY
CLKIN
PLL
5u to 64u
VCO
÷ 1, 2, 4, 8
÷ 1 to 15
CCLK
SCLK
SCLK d CCLK
Figure 7. Frequency Modification Methods
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15. Table 6 illustrates typical system clock ratios.
Note that the divisor ratio must be chosen to limit the system
clock frequency to its maximum of f_SCLK. The SSEL value can be
dynamically changed without any PLL lock latencies by writing
the appropriate values to the PLL divisor register (PLL_DIV)
using the bfrom_SysControl() function in the on-chip ROM.
Table 6. Example System Clock Ratios
Signal Name
SSEL3–0
0001
0110
1010
Example Frequency Ratios
Divider Ratio
(MHz)
VCO/SCLK VCO
SCLK
1:1
100
100
6:1
300
50
10:1
500
50
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL1–0 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in
Table 7. This programmable core clock capability is useful for
fast core frequency modifications.
Table 7. Core Clock Ratios
Signal Name
CSEL1–0
00
01
10
11
Example Frequency Ratios
Divider Ratio
(MHz)
VCO/CCLK VCO
CCLK
1:1
300
300
2:1
300
150
4:1
500
125
8:1
200
25
Rev. D | Page 17 of 88 | July 2013