ADSP-BF524_15 Datasheet, PDF (16/88 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
ADSP-BF523/ADSP-BF525/ADSP-BF527
VOLTAGE REGULATION
The ADSP-BF523/ADSP-BF525/ADSP-BF527 provides an on-
chip voltage regulator that can generate processor core voltage
levels from an external supply. Figure 5 shows the typical exter-
nal components required to complete the power management
system.
2.25V TO 3.6V
INPUT VOLTAGE
RANGE
V_DDEXT
(LOW-INDUCTANCE)
SET OF DECOUPLING
CAPACITORS
100μF
+
100nF
FDS9431A
10μ F
LOW ESR
+
100μF
10μH
+
ZHCS1000 100μF
V_DDEXT
V_DDINT
SS/PG
SHORT AND LOW-
INDUCTANCE WIRE
SEE H/W REFERENCE,
SYSTEM DESIGN CHAPTER,
TO DETERMINE VALUE
NOTE: DESIGNER SHOULD MINIMIZE
TRACE LENGTH TO FDS9431A.
VR_OUT
EXT_WAKE1
VR_SEL
GND
Figure 5. ADSP-BF523/ADSP-BF525/ADSP-BF527 Voltage Regulator Circuit
The regulator controls the internal logic voltage levels and is
programmable with the voltage regulator control register
(VR_CTL) in increments of 50 mV. This register can be
accessed using the bfrom_SysControl() function in the on-chip
ROM. To reduce standby power consumption, the internal volt-
age regulator can be programmed to remove power to the
processor core while keeping I/O power supplied. While in the
hibernate state, all external supplies (V_DDEXT, V_DDMEM, V_DDUSB,
V_DDOTP) can still be applied, eliminating the need for external
buffers. V_DDRTC must be applied at all times for correct hibernate
operation. The voltage regulator can be activated from this
power-down state either through an RTC wakeup, a USB wake-
up, an Ethernet wake-up, or by asserting the RESET pin, each of
which then initiates a boot sequence. The regulator can also be
disabled and bypassed at the user’s discretion.
The voltage regulator has two modes set by the VR_SEL pin—the
normal pulse width control of an external FET and the external
supply mode which can signal a power down during hibernate
to an external regulator. Set VR_SEL to V_DDEXT to use an external
regulator or set VR_SEL to GND to use the internal regulator. In
the external mode VR_OUT becomes EXT_WAKE1. If the internal
regulator is used, EXT_WAKE0 can control other power
sources in the system during the hibernate state. Both signals
are high-true for power-up and may be connected directly to the
low-true shutdown input of many common regulators. The
mode of the SS/PG (Soft Start/Power Good) signal also changes
according to the state of VR_SEL. When using an internal regula-
tor, the SS/PG pin is Soft Start, and when using an external
regulator, it is Power Good. The Soft Start feature is recom-
mended to reduce the inrush currents and to reduce V_DDINT
voltage overshoot when coming out of hibernate or changing
voltage levels. The Power Good (PG) input signal allows the
processor to start only after the internal voltage has reached a
chosen level. In this way, the startup time of the external
regulator is detected after hibernation. For a complete
description of Soft Start and Power Good functionality, refer
to the ADSP-BF52x Blackfin Processor Hardware Reference.
ADSP-BF522/ADSP-BF524/ADSP-BF526
VOLTAGE REGULATION
The ADSP-BF522/ADSP-BF524/ADSP-BF526 processor
requires an external voltage regulator to power the V_DDINT
domain. To reduce standby power consumption, the external
voltage regulator can be signaled through EXT_WAKE0 or
EXT_WAKE1 to remove power from the processor core. These
identical signals are high-true for power-up and may be con-
nected directly to the low-true shut down input of many
common regulators. While in the hibernate state, all external
supplies (V_DDEXT, V_DDMEM, V_DDUSB, V_DDOTP) can still be applied,
eliminating the need for external buffers. V_DDRTC must be
applied at all times for correct hibernate operation. The external
voltage regulator can be activated from this power down state
either through an RTC wakeup, a USB wakeup, an Ethernet
wakeup, or by asserting the RESET pin, each of which then initi-
ates a boot sequence. EXT_WAKE0 or EXT_WAKE1 indicate a
wakeup to the external voltage regulator. The Power Good (PG)
input signal allows the processor to start only after the internal
voltage has reached a chosen level. In this way, the startup time
of the external regulator is detected after hibernation. For a
complete description of the Power Good functionality, refer to
the ADSP-BF52x Blackfin Processor Hardware Reference.
CLOCK SIGNALS
The processor can be clocked by an external crystal, a sine wave
input, or a buffered, shaped clock derived from an external
clock oscillator.
If an external clock is used, it should be a TTL compatible signal
and must not be halted, changed, or operated below the speci-
fied frequency during normal operation. This signal is
connected to the processor’s CLKIN pin. When an external
clock is used, the XTAL pin must be left unconnected.
Alternatively, because the processor includes an on-chip oscilla-
tor circuit, an external crystal may be used. For fundamental
frequency operation, use the circuit shown in Figure 6. A
parallel-resonant, fundamental frequency, microprocessor-
grade crystal is connected across the CLKIN and XTAL pins.
The on-chip resistance between CLKIN and the XTAL pin is in
the 500 kΩ range. Further parallel resistors are typically not rec-
ommended. The two capacitors and the series resistor shown in
Figure 6 fine tune phase and amplitude of the sine frequency.
The capacitor and resistor values shown in Figure 6 are typical
values only. The capacitor values are dependent upon the crystal
manufacturers’ load capacitance recommendations and the PCB
physical layout. The resistor value depends on the drive level
Rev. D | Page 16 of 88 | July 2013