ADSP-2184_15 Datasheet, PDF (17/31 Pages) Analog Devices – DSP Microcomputer

ADSP-2184
Parameter
Min
Max
Unit
Bus Request–Bus Grant
Timing Requirements:
t_BH
BR Hold after CLKOUT High¹
t_BS
BR Setup before CLKOUT Low¹
Switching Characteristics:
t_SD
CLKOUT High to xMS, RD, WR Disable
t_SDB
xMS, RD, WR Disable to BG Low
t_SE
BG High to xMS, RD, WR Enable
t_SEC
xMS, RD, WR Enable to CLKOUT High
t_SDBH
xMS, RD, WR Disable to BGH Low²
t_SEH
BGH High to xMS, RD, WR Enable²
0.25 t_CK + 2
ns
0.25 t_CK + 17
ns
0.25 t_CK + 10
ns
0
ns
0
ns
0.25 t_CK – 7
ns
0
ns
0
ns
NOTES
xMS = PMS, DMS, CMS, IOMS, BMS.
1_{BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on}
the following cycle. Refer to the ADSP-2100 Family User’s Manual, Third Edition, for BR/BG cycle relationships.
2_{BGH is asserted when the bus is granted and the processor requires control of the bus to continue.}
t_BH
CLKOUT
BR
CLKOUT
PMS, DMS
BMS, RD
WR
BG
BGH
t_BS
t_SD
t_SEC
t_SDB
t_SE
t_SDBH
t_SEH
Figure 11.␣ Bus Request–Bus Grant
REV. 0
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