AD9841A_15 Datasheet, PDF (17/23 Pages) Analog Devices – Complete 20 MSPS CCD Signal Processors

AD9841A/AD9842A
Table IV. AD9841A Clamp Level Register Contents (Default Value x080)
MSB
LSB
D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
•
•
•
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
Clamp Level (LSB)
0
0.25
0.5
•
•
•
63.5
63.75
Table V. AD9842A Clamp Level Register Contents (Default Value x080)
MSB
LSB
D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
•
•
•
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
Clamp Level (LSB)
0
1
2
•
•
•
254
255
Table VI. Control Register Contents (Default Value x000)
Data Out
D10 D9
DATACLK
D8 D7 D6
CLP/PBLK SHP/SHD
D5
D4
PxGA
D3**
Color Steering Modes
D2 D1 D0
X 0 Enable
0* 0* 0 Rising Edge Trigger 0 Active Low 0 Active Low 0 Disable 0 0 0 Steering Disabled
1 Three-State
1 Falling Edge Trigger 1 Active High 1 Active High 1 Enable 0 0 1 Mosaic Separate
0 1 0 Interlace
0 1 1 3-Color
1 0 0 4-Color
1 0 1 VD Selected
1 1 0 Mosaic Repeat
1 1 1 User Specified
*Must be set to zero.
**When D3 = 0 (PxGA disabled) the PxGA gain is fixed to 4 dB.
Table VII. PxGA Gain Registers for Gain0, Gain1, Gain2, Gain3 (Default Value x000)
MSB
LSB
D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
0
1
1
1
1
1
•
•
•
0
0
0
0
0
0
1
1
1
1
1
1
•
•
•
1
0
0
0
0
0
*Control Register Bit D3 must be set High (PxGA Enable) to use the PxGA Gain Registers.
Gain (dB)*
+10.0
•
•
•
+4.3
+4.0
•
•
•
–2.0
REV. 0
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