AD9841A_15 Datasheet, PDF (13/23 Pages) Analog Devices – Complete 20 MSPS CCD Signal Processors

AD9841A/AD9842A
VD
EVEN FIELD
0101...
0101...
0101...
2323...
ODD FIELD
2323...
2323...
HD
LINE 0
LINE 1
LINE 2
LINE m–1
LINE m
LINE 0
LINE 1
LINE 2
LINE m–1
NOTE: 0 = GAIN0, 1 = GAIN1, 2 = GAIN2, 3 = GAIN3
Figure 16. PxGA Mode 5 (VD Selected) Frame/Line Gain Register Sequence
LINE m
VD
HD
3ns MIN
5 PIXEL MIN
3ns MIN
SHP
PxGA GAIN
GAINX
GAIN0 GAIN1 GAIN0
GAINX GAIN2
NOTES:
1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES.
2. EVERY HD RISING EDGE WITH A PREVIOUS VD FALLING EDGE WILL RESET TO 0101.
3. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 2323.
4. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL REPEAT EITHER 0101... (EVEN) OR 2323 ... (ODD).
GAIN3
Figure 17. PxGA Mode 5 (VD Selected) Detailed Timing
VD
FRAME n
FRAME n+1
0101...
1212...
0101...
0101...
1212...
0101...
HD
LINE 0
LINE 1
LINE 2
LINE m–1
LINE m
LINE 0
LINE 1
LINE 2
LINE m–1
NOTE: 0 = GAIN0, 1 = GAIN1, 2 = GAIN2
Figure 18. PxGA Mode 6 (Mosaic Repeat) Frame/Line Gain Register Sequence
LINE m
5 PIXEL MIN
VD
HD
3ns MIN
3ns MIN
SHP
PxGA GAIN
GAINX
GAIN0
GAIN1 GAIN0 GAINX
NOTES:
1. MINIMUM PULSEWIDTH FOR HD AND VD IS 5 PIXEL CYCLES.
2. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES. MINIMUM SET-UP TIME IS 3ns.
3. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 0101.
4. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL ALTERNATE BETWEEN 0101... AND 1212.
Figure 19. PxGA Mode 6 (Mosaic Repeat) Detailed Timing
GAIN1
GAIN2
REV. 0
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