AD7176-2 Datasheet, PDF (17/68 Pages) Analog Devices – The AD7176-2 is a fast settling, highly accurate, high resolution, multiplexed Σ-Δ analog-to-digital converter (ADC) for low band-width input signals.

Data Sheet
AD7176-2
The linear regulator for the digital IOVDD supply performs a
similar function, regulating the input voltage applied at the
IOVDD pin to 2 V for the internal digital filtering. The serial
interface signals always operate from the IOVDD supply seen at
the pin. This means that if 3.3 V is applied to the IOVDD pin,
the interface logic inputs and outputs operate at this level.
The AD7176-2 can be used across a wide variety of applications,
providing high resolution and accuracy. A sample of these
scenarios is as follows:
• Fast scanning of analog input channels using the internal
multiplexer.
• Fast scanning of analog input channels using an external
multiplexer.
• High resolution at lower speeds in either channel scanning
or ADC per channel applications.
• Single ADC per channel: the fast low latency output allows
further application specific filtering in an external micro-
controller, DSP, or FPGA.
POWER SUPPLIES
The AD7176-2 has three independent power supply pins:
AVDD1, AVDD2, and IOVDD.
AVDD1 powers the front-end circuitry, including the crosspoint
multiplexer. AVDD1 is referenced to AVSS and AVDD1 − AVSS
= 5 V only. This can be a single 5 V supply or a ±2.5 V split
supply. The split supply operation allows for true bipolar inputs.
When using split supplies, the absolute maximum ratings (see
the Absolute Maximum Ratings section) must be kept in mind.
AVDD2 powers the internal 1.8 V analog LDO regulator. This
regulator powers the ADC core. AVDD2 is referenced to AVSS,
and AVDD2 – AVSS can range from 5 V to 2 V.
IOVDD powers the internal 1.8 V digital LDO regulator. This
regulator powers the digital logic of the ADC. IOVDD sets the
voltage levels for the SPI interface of the ADC. IOVDD is refer-
enced to DGND, and IOVDD − DGND can vary from 5 V to 2 V.
DIGITAL COMMUNICATION
The AD7176-2 has a 3- or 4-wire SPI interface that is compatible
with QSPI™, MICROWIRE®, and DSPs. The interface operates
in SPI Mode 3 and can be operated with CS tied low. In SPI
Mode 3, the SCLK idles high, the falling edge of SCLK is the
drive edge, and the rising edge of SCLK is the sample edge. This
means that data is clocked out on the falling/drive edge and data
is clocked in on the rising/sample edge.
DRIVE EDGE
SAMPLE EDGE
Accessing the ADC Register Map
The communications register controls access to the full register
map of the ADC. This register is an 8-bit write only register. On
power-up or after a reset, the digital interface defaults to a state
where it is expected a write to the communications register;
therefore, all communication begins by writing to the
communications register.
The data written to the communications register determines
which register is being accessed and if the next operation is a
read or write. The register address bits (RA[5:0]) determine the
specific register to which the read or write operation applies.
When the read or write operation to the selected register is
complete, the interface returns to its defaults state, where it
expects a write operation to the communications register.
In situations where interface synchronization is lost, a write
operation of at least 64 serial clock cycles with DIN high returns
the ADC to its default state by resetting the entire part, including
the register contents. Alternatively, if CS is being used with the
digital interface, returning CS high sets the digital interface to
its default state and aborts any current operation.
Figure 26 and Figure 27 illustrate writing to and reading from a
register by first writing the 8-bit command to the communications
register followed by the data for that register.
8-BIT COMMAND
8 BITS, 16 BITS,
OR 24 BITS OF DATA
CS
DIN
CMD
DATA
SCLK
Figure 26. Writing to a Register
(8-Bit Command with Register Address Followed by Data of 8, 16, or 24 Bits;
Data Length Is Dependent on the Register Selected)
8-BIT COMMAND
8 BITS, 16 BITS,
24 BITS, OR
32 BITS OF DATA
CS
DIN
DOUT/RDY
CMD
DATA
SCLK
Figure 25. SPI Mode 3 SCLK Edges
Figure 27. Reading from a Register
(8-Bit Command with Register Address Followed by Data of 8, 16, or 24 Bits;
Data Length on DOUT Is Dependent on the Register Selected)
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