AD5339_15 Datasheet, PDF (17/28 Pages) Analog Devices – 2.5 V to 5.5 V, 250A, 2-Wire Interface, Dual Voltage Output, 8-/10-/12-Bit DACs

AD5337/AD5338/AD5339
Default Readback Condition
All pointer byte bits power up to 0. Therefore, if the user
initiates a readback without writing to the pointer byte first, no
single DAC channel has been specified. In this case, the default
readback bits are all 0s, except for the CLR bit, which is 1.
Multiple DAC Write Sequence
Because there are individual bits in the pointer byte for each
DAC, it is possible to write the same data and control bits to two
DACs simultaneously by setting the relevant bits to 1.
Multiple DAC Read Back Sequence
If the user attempts to read back data from more than one DAC
at a time, the part reads back the default, power-on reset
conditions, that is, all 0s except for CLR, which is 1.
WRITE OPERATION
When writing to the AD5337/AD5338/AD5339 DACs, the user
must begin with an address byte (R/W = 0), after which the
DAC acknowledges that it is prepared to receive data by pulling
SDA low. This address byte is followed by the pointer byte,
which is also acknowledged by the DAC. Two bytes of data are
then written to the DAC, as shown in Figure 33. A stop
condition follows.
MSB
PD1
MOST SIGNIFICANT DATA BYTE
8-BIT AD5337
PD0 CLR LDAC D7 D6 D5
LSB
D4
MSB
D3
LEAST SIGNIFICANT DATA BYTE
8-BIT AD5337
D2 D1 D0 X
X
X
LSB
X
MSB
10-BIT AD5338
PD1 PD0 CLR LDAC D9 D8
LSB
D7 D6
MSB
D5 D4
10-BIT AD5338
D3 D2 D1 D0
LSB
X
X
MSB
12-BIT AD5339
LSB
PD1 PD0 CLR LDAC D11 D10 D9 D8
MSB
D7 D6
12-BIT AD5339
D5 D4 D3 D2
Figure 32. Data Formats for Write and Read Back
LSB
D1 D0
SCL
SDA
0
0
0
1
1
0
A0
R/W
X
X
START
CONDITION
BY
MASTER
ADDRESS BYTE
ACK MSB
BY
AD533x
POINTER BYTE
LSB
ACK
BY
AD533x
SCL
SDA
MSB
MOST SIGNIFICANT DATA BYTE
LSB
ACK
BY
AD533x
MSB
LEAST SIGNIFICANT DATA BYTE
Figure 33. Write Sequence
LSB
ACK
BY
AD533x
STOP
CONDITION
BY
MASTER
Rev. C | Page 17 of 28