OP249_07 Datasheet, PDF (16/20 Pages) Analog Devices – Dual, Precision JFET High Speed Operational Amplifier

OP249
100
90
A
4µs
100
90
B
4µs
10
10
0%
0%
500mV
1µs
500mV
1µs
C = 5pF
RESPONSE IS GROSSLY UNDERDAMPED,
AND EXHIBITS RINGING
C = 15pF
FAST RISE TIME CHARACTERISTICS, BUT AT EXPENSE
OF SLIGHT PEAKING IN RESPONSE
Figure 49. Effect of Altering Compensation from Circuit in Figure 47—PM7545 CMOS DAC with 1/2 OP249, Unipolar Operation;
Critically Damped Response Is Obtained with C ≈ 33 pF
Figure 49 illustrates the effect of altering the compensation on
the output response of the circuit in Figure 47. Compensation is
required to address the combined effect of the output capacitance
of the DAC, the input capacitance of the op amp, and any stray
capacitance. Slight adjustments to the compensation capacitor
may be required to optimize settling response for any given
application.
Figure 50 shows a settling measurement circuit for evaluating
recovery from an output current transient. An output disturbing
current generator provides the transient change in output load
current of 1 mA.
+15V _0.1µF
The settling time of the combination of the current output DAC
and the op amp can be approximated by
( ) ( ) t _S TOTAL = t _S DAC ² + t_S AMP ²
The actual overall settling time is affected by the noise gain of
the amplifier, the applied compensation, and the equivalent
input capacitance at the input of the amplifier.
DISSCUSION ON DRIVING ADCs
Settling characteristics of op amps also include the ability of the
amplifier to recover, that is, settle, from a transient current output
load condition. An example of this includes an op amp driving
the input from a SAR-type ADC. Although the comparison
point of the converter is usually diode clamped, the input swing
of plus-and-minus a diode drop still gives rise to a significant
modulation of input current. If the closed-loop output impedance
is low enough and bandwidth of the amplifier is sufficiently
large, the output settles before the converter makes a comparison
decision, which prevents linearity errors or missing codes.
3
8
1/2
OP249
2
4
1
0.1µF
7A13 PLUG-IN
*
–15V
7A13 PLUG-IN
300pF
+15V
1kΩ
ΔI_OUT
=
|V_REF|
1kΩ
TTL INPUT
+15V
1.5kΩ
1N4148
1.8kΩ
2N2907
220Ω
2N3904
1kΩ
10µF
0.1µF
0.01µF
*
0.47µF
*DECOUPLE CLOSE TOGETHER ON GROUND
PLANE WITH SHORT LEAD LENGTHS.
V_REF
Figure 50. Transient Output Impedance Test Fixture
Rev. F | Page 16 of 20