AD9381_15 Datasheet, PDF (16/44 Pages) Analog Devices – HDMI Display Interface

AD9381
Hex
Address
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
Read/Write
or Read Only Bits
Default Value Register Name
Description
[2:0] *****000
Interlace Offset
Sets the difference (in HSYNCs) in field length
between Field 0 and Field 1.
Read/Write
[7:2] 011000**
VS Delay
Sets the delay (in lines) from the VSYNC leading
edge to the start of active video.
[1:0] ******01
HS Delay MSB
MSB, Register 0x29.
Read/Write
[7:0] 00000100
HS Delay
Sets the delay (in pixels) from the HSYNC leading
edge to the start of active video.
Read/Write
[3:0] ****0101
Line Width MSB
MSB, Register 0x2B.
Read/Write
[7:0] 00000000
Line Width
Sets the width of the active video line in pixels.
Read/Write
[3:0] ****0010
Screen Height MSB
MSB, Register 0x2D.
Read/Write
[7:0] 11010000
Screen Height
Sets the height of the active screen in lines.
Read/Write
[7]
0*******
Ctrl EN
Allows Ctrl [3:0] to be output on the I²S data pins.
00 = I²S mode.
[6:5] *00*****
I2S Out Mode
01 = right-justified.
10 = left-justified.
11 = raw IEC60958 mode.
[4:0] ***11000
I2S Bit Width
Sets the desired bit width for right-justified mode.
Read
[6]
*0******
TMDS Sync Detect
Detects a TMDS DE.
[5] **0*****
TMDS Active
Detects a TMDS clock.
[4]
***0****
AV Mute
Gives the status of AV mute based on general
control packets.
[3]
****0***
HDCP Keys Read
Returns 1 when read of EEPROM keys is successful.
[2:0] *****000
HDMI Quality
Returns quality number based on DE edges.
Read
[6] *0******
HDMI Content Encrypted
This bit is high when HDCP decryption is in use
(content is protected). The signal goes low when
HDCP is not being used. Customers can use this bit
to allow copying of the content. The bit should be
sampled at regular intervals because it can change
on a frame-by-frame basis.
[5] **0*****
DVI HSYNC Polarity
Returns DVI HSYNC polarity.
[4]
***0****
DVI VSYNC Polarity
Returns DVI VSYNC polarity.
[3:0] ****0000
HDMI Pixel Repetition
Returns current HDMI pixel repetition amount.
0 = 1×, 1 = 2×, ... .The clock and data outputs
automatically de-repeat by this value.
Read/Write
[7:4] 1001****
MV Pulse Max
Sets the maximum pseudo sync pulse width for
Macrovision® detection.
[3:0] ****0110
MV Pulse Min
Sets the minimum pseudo sync pulse width for
Macrovision detection.
Read/Write
[7]
0*******
MV Oversample En
Tells the Macrovision detection engine whether we
are oversampling or not.
[6] *0******
MV Pal En
Tells the Macrovision detection engine to enter PAL
mode.
[5:0] **001101
MV Line Count Start
Sets the start line for Macrovision detection.
Read/Write
[7]
1*******
MV Detect Mode
0 = standard definition.
1 = progressive scan mode.
[6] *0******
MV Settings Override
0 = use hard-coded settings for line counts and
pulse widths.
1 = use I²C values for these settings.
[5:0] **010101
MV Line Count End
Sets the end line for Macrovision detection.
Read/Write
[7:6] 10******
MV Pulse Limit Set
Sets the number of pulses required in the last 3
lines (SD mode only).
[5] **0*****
Low Freq Mode
Sets audio PLL to low frequency mode. Low
frequency mode should only be set for pixel clocks
<80 MHz.
Rev. 0 | Page 16 of 44