DAC8413_15 Datasheet, PDF (15/20 Pages) Analog Devices – Quad, 12-Bit DAC Voltage Output with Readback

Data Sheet
RESET
The RESET function can be used either at power-up or at any
time during DAC operation. The RESET function is independent
of CS. This pin is active low and sets the DAC output registers
to either center code for the DAC8412, or zero code for the
DAC8413. The reset-to-center code is most useful when the
DAC is configured for bipolar references and an output of 0 V
after reset is desired.
SUPPLIES
Supplies required are VSS, VDD, and VLOGIC. The VSS supply can
be set between −15 V and 0 V. VDD is the positive supply; its
operating range is between 5 V and 15 V.
DAC8412/DAC8413
VLOGIC is the digital output supply voltage for the readback
function. It is normally connected to +5 V. This pin is a logic
reference input only. It does not supply current to the device. If
the readback function is not being used, VLOGIC can be left open-
circuit. While VLOGIC does not supply current to the DAC8412, it
does supply currents to the digital outputs when readback is used.
AMPLIFIERS
Unlike many voltage output DACs, the DAC8412 features buffered
voltage outputs. Each output is capable of both sourcing and
sinking 5 mA at ±10 V, eliminating the need for external
amplifiers when driving 500 pF or smaller capacitive load in
most applications. These amplifiers are short-circuit protected.
Table 6. DAC8412/DAC8413 Logic Table
A1 A0 R/W CS RS LDAC
L
L
L
L
HL
L
HL
L
HL
H
L
L
L
HL
HHL
L
HL
L
L
L
L
HH
L
HL
L
HH
H
L
L
L
HH
HHL
L
HH
L
L
H
L
HH
L
HH
L
HH
H
L
H
L
HH
HHH
L
HH
X
X
X
HHL
X
X
X
HHH
X
X
X
X
L
X
X
X
X
H
X
Input Register
Output Register
Write
Write
Write
Write
Write
Write
Write
Write
Write
Hold
Write
Hold
Write
Hold
Write
Hold
Read
Hold
Read
Hold
Read
Hold
Read
Hold
Hold
Update all output registers
Hold
Hold
All registers reset to midscale/zero-scale¹
All registers latched to midscale/zero-scale¹
Mode
DAC
Transparent
A
Transparent
B
Transparent
C
Transparent
D
Write input
A
Write input
B
Write input
C
Write input
D
Read input
A
Read input
B
Read input
C
Read input
D
All
Hold
All
All
All
1 _{DAC8412 resets to midscale, and DAC8413 resets to zero scale. L = logic low; H = logic high; X = don’t care. Input and output registers are transparent when asserted.}
Rev. G | Page 15 of 20