DAC8413_15 Datasheet, PDF (11/20 Pages) Analog Devices – Quad, 12-Bit DAC Voltage Output with Readback

Data Sheet
10V
1V/DIV
EA
TRIG'D
0V
–580ns
15.5mV
0
INPUT
–5V
2mV/DIV
5V/DIV
TRIG'D
V_DD = +15V
V_SS = –15V
V_REFH = +10V
V_REFL = –10V
T_A = 25°C
1µs/DIV
Figure 22. Positive Slew Rate
9.42µs
V_DD = +15V
V_SS = –15V
V_REFH = +10V
V_REFL = –10V
T_A = 25°C
–4.5mV
–1.96µs
32.5mV
5V
INPUT
0
2µs/DIV
Figure 23. Settling Time (Negative)
18.04µs
5mV/DIV
5V/DIV
TRIG'D
–17.5mV
–1.96µs
1 LSB ERROR BAND
2µs/DIV
V_DD = +15V
V_SS = –15V
V_REFH = +10V
V_REFL = –10V
T_A = 25°C
18.04µs
Figure 24. Settling Time (Positive)
DAC8412/DAC8413
10V
1V/DIV
EA
TRIG'D
V_DD = +15V
V_SS = –15V
V_REFH = +10V
V_REFL = –10V
T_A = 25°C
0V
–580ns
1µs/DIV
Figure 25. Negative Slew Rate
2.0 _{VDD = +15V}
V_SS = –15V
V_REFH = +10V
1.5 VREFL = –10V
T_A = 25°C
1.0
9.42µs
0.5
0
–0.5
0
511 1023 1535 2047 2559 3071 3583 4095
DIGITAL INPUT CODE (Decimal)
Figure 26. IVREFH vs. Code
1.0
V_DD = +15V
V_SS = –15V
0.8 V_REFH = +10V
V_REFL = –10V
T_A = 25°C
0.6
0.4
0.2
0
–0.2
0.01
0.1
1
10
100
LOAD RESISTANCE (kΩ)
Figure 27. INL vs. Load Resistance
Rev. G | Page 11 of 20