AD9258BCPZ-80 Datasheet, PDF (15/44 Pages) Analog Devices – 14-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)

AD9258
CLK+ 1
CLK– 2
SYNC 3
NC 4
NC 5
NC 6
NC 7
D0– (LSB) 8
D0+ (LSB) 9
DRVDD 10
D1– 11
D1+ 12
D2– 13
D2+ 14
D3– 15
D3+ 16
PIN 1
INDICATOR
AD9258
PARALLEL LVDS
TOP VIEW
(Not to Scale)
48 PDWN
47 OEB
46 CSB
45 SCLK/DFS
44 SDIO/DCS
43 OR+
42 OR–
41 D13+ (MSB)
40 D13– (MSB)
39 D12+
38 D12–
37 DRVDD
36 D11+
35 D11–
34 D10+
33 D10–
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE
PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED
PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.
Figure 7. LFCSP Interleaved Parallel LVDS Pin Configuration (Top View)
Table 9. Pin Function Descriptions (Interleaved Parallel LVDS Mode)
Pin No.
Mnemonic Type
Description
ADC Power Supplies
10, 19, 28, 37
DRVDD
Supply
Digital Output Driver Supply (1.8 V Nominal).
49, 50, 53, 54, 59,
60, 63, 64
AVDD
Supply
Analog Power Supply (1.8 V Nominal).
4, 5, 6, 7
NC
Do Not Connect.
0
AGND,
Ground
The exposed thermal pad on the bottom of the package provides the analog
Exposed Pad
ground for the part. This exposed pad must be connected to ground for proper
operation.
ADC Analog
51
VIN+A
Input
Differential Analog Input Pin (+) for Channel A.
52
VIN−A
Input
Differential Analog Input Pin (−) for Channel A.
62
VIN+B
Input
Differential Analog Input Pin (+) for Channel B.
61
VIN−B
Input
Differential Analog Input Pin (−) for Channel B.
55
VREF
Input/Output Voltage Reference Input/Output.
56
SENSE
Input
Voltage Reference Mode Select. See Table 11 for details.
58
RBIAS
Input/Output External Reference Bias Resistor.
57
VCM
Output
Common-Mode Level Bias Output for Analog Inputs.
1
CLK+
Input
ADC Clock Input—True.
2
CLK−
Input
ADC Clock Input—Complement.
Digital Input
3
SYNC
Input
Digital Synchronization Pin. Slave mode only.
Digital Outputs
9
D0+ (LSB)
Output
Channel A/Channel B LVDS Output Data 0—True.
8
D0− (LSB)
Output
Channel A/Channel B LVDS Output Data 0—Complement.
12
D1+
Output
Channel A/Channel B LVDS Output Data 1—True.
11
D1−
Output
Channel A/Channel B LVDS Output Data 1—Complement.
14
D2+
Output
Channel A/Channel B LVDS Output Data 2—True.
13
D2−
Output
Channel A/Channel B LVDS Output Data 2—Complement.
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