AD5533_15 Datasheet, PDF (14/16 Pages) Analog Devices – 32-Channel Infinite Sample-and-Hold

AD5533
MICROPROCESSOR INTERFACING
AD5533 to ADSP-21xx Interface
The ADSP-21xx family of DSPs are easily interfaced to the
AD5533 without the need for extra logic.
A data transfer is initiated by writing a word to the Tx Register
after the SPORT has been enabled. In a write sequence, data is
clocked out on each rising edge of the DSP’s serial clock and
clocked into the AD5533 on the falling edge of its SCLK. In
read back, 16 bits of data are clocked out of the AD5533 on each
rising edge of SCLK and clocked into the DSP on the rising edge of
SCLK. D_IN is ignored. The valid 14 bits of data will be centered
in the 16-bit Rx Register when using this configuration. The
SPORT Control Register should be set up as follows:
TFSW = RFSW = 1, Alternate Framing
INVRFS = INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right Justify Data
ISCLK = 1, Internal Serial Clock
TFSR = RFSR = 1, Frame Every Word
IRFS = 0, External Framing Signal
ITFS = 1, Internal Framing Signal
SLEN = 1001, 10-Bit Data-Words (ISHA Mode Write)
SLEN = 1111, 16-Bit Data-Words (Readback Mode)
Figure 9 shows the connection diagram.
AD5533*
D_OUT
SYNC
D_IN
SCLK
ADSP-2101/
DR ^ADSP-2103*
TFS
RFS
DT
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 9. AD5533 to ADSP-2101/ADSP-2103 Interface
AD5533 to MC68HC11
The Serial Peripheral Interface (SPI) on the MC68HC11 is
configured for Master Mode (MSTR) = 1, Clock Polarity Bit
(CPOL) = 0, and the Clock Phase Bit (CPHA) = 1. The SPI is
configured by writing to the SPI Control Register (SPCR)—see
68HC11 User Manual. SCK of the 68HC11 drives the SCLK of
the AD5533, the MOSI output drives the serial data line (D_IN)
of the AD5533, and the MISO input is driven from D_OUT. The
SYNC signal is derived from a port line (PC7). When data is
being transmitted to the AD5533, the SYNC line is taken low
(PC7). Data appearing on the MOSI output is valid on the falling
edge of SCK. Serial data from the 68HC11 is transmitted in
8-bit bytes with only eight falling clock edges occurring in the
transmit cycle. Data is transmitted MSB first. To transmit 10 data
bits in ISHA Mode, it is important to left-justify the data in the
SPDR Register. PC7 must be pulled low to start a transfer. It is
taken high and pulled low again before any further read/write cycles
can take place. A connection diagram is shown in Figure 10.
AD5533*
D_OUT
SYNC
SCLK
D_IN
MC68HC11*
MISO
PC7
SCK
MOSI
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 10. AD5533 to MC68HC11 Interface
AD5533 to PIC16C6x/PIC16C7x
The PIC16C6x Synchronous Serial Port (SSP) is configured as an
SPI Master with the Clock Polarity Bit = 0. This is done by writing
to the Synchronous Serial Port Control Register (SSPCON). See
PIC16/PIC17 Microcontroller User Manual. In this example, I/O port
RA1 is being used to pulse SYNC and enable the serial port of
the AD5533. This microcontroller transfers only eight bits of data
during each serial transfer operation; therefore, two consecutive
read/write operations are needed for a 10-bit write and a 14-bit
read back. Figure 11 shows the connection diagram.
AD5533*
SCLK
D_OUT
D_IN
SYNC
PIC16C6x/7x*
SCK/RC3
SDO/RC5
SDI/RC4
RA1
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 11. AD5533 to PIC16C6x/7x Interface
AD5533 to 8051
The AD5533 requires a clock synchronized to the serial data.
The 8051 serial interface must therefore be operated in Mode 0.
In this mode, serial data enters and exits through RxD and a
shift clock is output on TxD. Figure 12 shows how the 8051 is
connected to the AD5533. Because the AD5533 shifts data
out on the rising edge of the shift clock and latches data in on
the falling edge, the shift clock must be inverted. The AD5533
requires its data with the MSB first. Since the 8051 outputs
the LSB first, the transmit routine must take this into account.
AD5533*
SCLK
D_OUT
D_IN
SYNC
8051*
TxD
RxD
P1.1
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 12. AD5533 to 8051 Interface
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REV. A