AD1847 Datasheet, PDF (14/28 Pages) Analog Devices – Serial-Port 16-Bit SoundPort Stereo Codec

AD1847
Left Auxiliary #2 Input Control Register (Index Address 4)
IA3:0
0100
Data 7
LMX2
Data 6
res
Data 5
res
Data 4
LX2G4
Data 3
LX2G3
Data 2
LX2G2
Data 1
LX2G1
Data 0
LX2G0
LX2G4:0 Left Auxiliary #2 Gain Select. The least significant bit of this 32-level gain/attenuate select represents –1.5 dB.
LX2G4:0 = 0 produces a +12 dB gain. LX2G4:0 = “01000” (8 decimal) produces 0 dB gain. Maximum attenuation is
–34.5 dB. Gains referred to 2.0 V p-p full-scale output level.
res
Reserved for future expansion. Write zeros (LO) to all reserved bits.
LMX2 Left Auxiliary #2 Mute. This bit, when set HI, will mute the left channel of the Auxiliary #2 input source. This bit is HI
after reset.
This register’s initial state after reset is: 1000 0000 (80h).
Right Auxiliary #2 Input Control Register (Index Address 5)
IA3:0
0101
Data 7
RMX2
Data 6
res
Data 5
res
Data 4
RX2G4
Data 3
RX2G3
Data 2
RX2G2
Data 1
RX2G1
Data 0
RX2G0
RX2G4:0 Right Auxiliary #2 Gain Select. The least significant bit of this 32-level gain/attenuate select represents –1.5 dB.
RX2G4:0 = 0 produces a +12 dB gain. RX2G4:0 = “01000” (8 decimal) produces 0 dB gain. Maximum attenuation is
–34.5 dB. Gains referred to 2.0 V p-p full-scale output level.
res
Reserved for future expansion. Write zeros (LO) to all reserved bits.
RMX2 Right Auxiliary #2 Mute. This bit, when set HI, will mute the right channel of the Auxiliary #2 input source. This bit is
HI after reset.
This register’s initial state after reset is: 1000 0000 (80h).
Left DAC Control Register (Index Address 6)
IA3:0
0110
Data 7
LDM
Data 6
res
Data 5
LDA5
Data 4
LDA4
Data 3
LDA3
Data 2
LDA2
Data 1
LDA1
Data 0
LDA0
LDA5:0 Left DAC Attenuate Select. The least significant bit of this 64-level attenuate select represents –1.5 dB. LDA5:0 = 0 pro-
duces a 0 dB attenuation. Maximum attenuation is –94.5 dB.
res
Reserved for future expansion. Write zeros (LO) to all reserved bits.
LDM
Left DAC Mute. This bit, when set HI, will mute the left channel output. Auxiliary inputs are muted independently with
the Left Auxiliary Input Control Registers. This bit is HI after reset.
This register’s initial state after reset is: 1000 0000 (80h).
Right DAC Control Register (Index Address 7)
IA3:0
0111
Data 7
RDM
Data 6
res
Data 5
RDA5
Data 4
RDA4
Data 3
RDA3
Data 2
RDA2
Data 1
RDA1
Data 0
RDA0
RDA5:0 Right DAC Attenuate Select. The least significant bit of this 64-level attenuate select represents –1.5 dB. RDA5:0 = 0
produces a 0 dB attenuation. Maximum attenuation must be at least –94.5 dB.
res
Reserved for future expansion. Write zeros (LO) to all reserved bits.
RDM
Right DAC Mute. This bit, when set HI, will mute the right DAC output. Auxiliary inputs are muted independently with
the Right Auxiliary Input Control Registers. This bit is HI after reset.
This register’s initial state after reset is: 1000 0000 (80h).
–14–
REV. B