AD1847 Datasheet, PDF (12/28 Pages) Analog Devices – Serial-Port 16-Bit SoundPort Stereo Codec

AD1847
Index Readback (16-Bit)
Data 15
CLOR
Data 7
DATA7
Data 14
MCE
Data 6
DATA6
Data 13
RREQ
Data 5
DATA5
Data 12
res
Data 4
DATA4
Data 11
IA3
Data 3
DATA3
Data 10
IA2
Data 2
DATA2
Data 9
IA1
Data 1
DATA1
Data 8
IA0
Data 0
DATA0
DATA7:0 Index Register Data. These bits are the readback data from the desired AD1847 Index Register referenced by the Index
Address from the previous Control Word (with the RREQ bit set). Read by the host CPU or DSP from the AD1847.
IA3:0
Index Register Address. These bits echo the indirect address (written during the previous Control Word (with the RREQ
bit set) of the desired AD1847 Index Register to be readback. Read by the host CPU or DSP from the AD1847.
RREQ
Read Request. This bit is set HI for Index Readback, echoing the RREQ state written by the host CPU or DSP in the
previous Control Word. Read by the host CPU or DSP from the AD1847.
res
Reserved for future expansion. All reserved bits read zero (LO).
MCE
Mode Change Enable. This bit echoes the MCE state written by the host CPU or DSP during the previous* Control
Word (with the RREQ bit set). Read by the host CPU or DSP from the AD1847.
CLOR
Clear Overrange. This bit echoes the CLOR state written by the host CPU or DSP during the previous Control Word
(with the RREQ bit set). Read by the host CPU or DSP from the AD1847.
Immediately after reset, the contents of this register is: 1110 0000 0000 0000 (E000h).
Indirect Mapped Registers
Following in Figure 6 is a table defining the mapping of AD1847 8-bit Index Registers to Index Address. These registers are accessed
by writing the appropriate 4-bit Index Address in the Control Word.
Index
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Register Name
Left Input Control
Right Input Control
Left Aux #1 Input Control
Right Aux #l Input Control
Left Aux #2 Input Control
Right Aux #2 Input Control
Left DAC Control
Right DAC Control
Data Format
Interface Configuration
Pin Control
Invalid Address
Miscellaneous Information
Digital Mix Control
Invalid Address
Invalid Address
Figure 6. Index Register Mapping
A detailed description of each of the Index Registers is given below.
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REV. B