AD9948 Datasheet, PDF (13/28 Pages) Analog Devices – 10-Bit CCD Signal Processor with Precision Timing TM Core

Address
00
Data Bit
Content
[1:0]
[2]
[3]
[4]
[5]
[7:6]
[8]
[9]
[11:10]
Default
Value
0
1
0
0
0
0
0
0
0
Table VIII. AFE Operation Register Detail
Name
PWRDOWN
CLPENABLE
CLPSPEED
FASTUPDATE
PBLK_LVL
TEST MODE
DCBYP
TESTMODE
CDSGAIN
Description
0 = Normal Operation.
1 = Reference Standby.
2/3 = Total Power-Down.
0 = Disable OB Clamp.
1 = Enable OB Clamp.
0 = Select Normal OB Clamp Settling.
1 = Select Fast OB Clamp Settling.
0 = Ignore VGA Update.
1 = Very Fast Clamping when VGA Is Updated.
DOUT Value during PBLK.
0 = Blank to Zero.
1 = Blank to Clamp Level.
Test Operation Only. Set to zero.
0 = Enable DC Restore Circuit.
1 = Bypass DC Restore Circuit during PBLK.
Test Operation Only. Set to zero.
Adjustment of CDS Gain.
0 = 0 dB.
01= –2 dB.
10 = –4 dB.
11 = 0 dB.
Table IX. AFE Control Register Detail
Address
04
Data Bit
Content
[1:0]
Default
Value
0
Name
COLORSTEER
[2]
1
PXGAENABLE
[3]
0
DOUTDISABLE
[4]
0
DOUTLATCH
[5]
0
GRAYENCODE
Description
0 = Off.
1 = Progressive.
2 = Interlaced.
3 = Three Field.
0 = Disable PxGA.
1 = Enable PxGA.
0 = Data Outputs Are Driven.
1 = Data Outputs Are Three-Stated.
0 = Latch Data Outputs with DOUT Phase.
1 = Output Latch Transparent.
0 = Binary Encode Data Outputs.
1= Gray Encode Data Outputs.
AD9948
REV. 0
–13–