AD9948 Datasheet, PDF (10/28 Pages) Analog Devices – 10-Bit CCD Signal Processor with Precision Timing TM Core

AD9948
Address
00
01
02
03
04
05
Data Bit
Content
[11:0]
[9:0]
[7:0]
[11:0]
[17:0]
[17:0]
Default
Value
4
0
80
4
0
0
Table II. AFE Register Map
Name
OPRMODE
VGAGAIN
CLAMP LEVEL
CTLMODE
PxGA GAIN01
PxGA GAIN23
Description
AFE Operation Modes. (See Table VIII.)
VGA Gain.
Optical Black Clamp Level.
AFE Control Modes. (See Table IX.)
PxGA Gain Registers for Color 0 [8:0] and Color 1 [17:9].
PxGA Gain Registers for Color 2 [8:0] and Color 3 [17:9].
Address
10
11
12
13
14
15
16
17
18
19
1A
Data Bit
Content
[0]
[0]
[0]
[11:0]
[0]
[0]
[1:0]
[0]
[1:0]
[0]
[0]
Default
Value
0
0
0
0
0
0
0
0
0
1
0
Table III. Miscellaneous Register Map
Name
SW_RST
OUT_CONTROL
TGCORE_RSTB
UPDATE
PREVENTUPDATE
VDHDEDGE
FIELDVAL
HBLKRETIME
CLPBLKOUT
CLPBLKEN
TEST MODE
Description
Software Reset.
1 = Reset all registers to default, then self-clear back to 0.
Output Control.
0 = Make all dc outputs inactive.
Timing Core Reset Bar.
0 = Reset TG core.
1 = Resume operation.
Serial Update.
Sets the line (HD) within the field to update serial data.
Prevents the update of the VD-Updated Registers.
1 = Prevent update.
VD/HD Active Edge.
0 = Falling edge triggered.
1 = Rising edge triggered.
Field Value Sync.
0 = Next Field 0.
1 = Next Field 1.
2/3 = Next Field 2.
Retime HBLK to Internal H1 Clock.
Preferred setting is 1. Setting to 1 will add one cycle delay to HBLK
toggle positions.
CLP/BLK Pin Output Select.
0 = CLPOB.
1 = PBLK.
2 = HBLK.
3 = Low.
Enable CLP/BLK Output.
1 = Enable.
Internal Test Mode.
Should always be set low.
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