AD9389_15 Datasheet, PDF (13/48 Pages) Analog Devices – 800 MHz High Performance HDMI/DVI Transmitter

AD9389
YCbCr 4:2:2 Formats (24 bits, 20 bits, or 16 bits) DDR with Separate Sync, Input ID = 6
An input format of YCbCr 4:2:2 DDR can be selected by setting the input ID (0x15[3:1]) to 0b110. The three different input pin
assignment styles are shown in Table 16. The input style can be set in 0x16[3:2]. The input CS (0x16[0]) must be set to 0b1. The data bit
width (12 bits, 10 bits, or 8 bits) must be set to with 0x16[5:4].
The 1^st or the 2^nd edge can be the rising or falling edge. The data input edge is defined in 0x16[1]. 0b0 = rising edge; 0b1 = falling edge.
Pixel 0 is the first pixel of the 4:2:2 word and should be where DE starts.
Table 16.
Input Format
YCbCr 4:2:2 Sep.
Syncs (DDR)
12-bit
YCbCr 4:2:2 Sep.
Syncs (DDR)
10-bit
YCbCr 4:2:2 Sep.
Syncs (DDR)
8-bit
12-bit
10-bit
8-bit
12-bit
10-bit
8-bit
Data[23:0]
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Style 1
1^st Pixel
OBSOLETE ^{2nd Pixel}
2^nd
Edge
1^st Edge
Style 2
Style 3
Y[7:4]
Cb[11:4]
Y[7:4]
Cr[11:4]
Y[5:4]
Cb[9:4]
Y[5:4]
Cr[9:4]
Cb[3:0]
Cb[7:4]
Cr[3:0]
Cr[7:4]
Cb[3:0]
Y[3:0]
Y[11:8]
Cr[3:0]
Cb[3:0]
Cr[3:0]
Y[3:0]
Y[7:4]
Y[3:0]
Y[7:4]
Y[3:0]
Y[9:6]
Y[3:0]
Y[9:6]
Y[3:0]
Y[11:8]
Y[11:0]
Cb[11:0]
Y[11:0]
Cr[11:0]
Y[9:0]
Cb[9:0]
Y[9:0]
Cr[9:0]
Y[7:0]
Cb[7:0]
Y[7:0]
Cr[7:0]
Cb[11:0]
Y[11:0]
Cr[11:0]
Y[11:0]
Cb[9:0]
Y[9:0]
Cr[9:0]
Y[9:0]
Cb[7:0]
Y[7:0]
Cr[7:0]
Y[7:0]
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