AD7175-8 Datasheet, PDF (13/64 Pages) Analog Devices – 24-Bit, 8-/16-Channel, 250 kSPS, Sigma- Delta ADC with True Rail-to-Rail Buffers

Data Sheet
0.000016
0.000014
ANALOG INPUT BUFFERS ON
ANALOG INPUT BUFFERS OFF
0.000012
0.000010
0.000008
0.000006
0.000004
0.000002
0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
INPUT COMMON-MODE VOLTAGE (V)
Figure 17. Noise vs. Input Common-Mode Voltage,
Analog Input Buffers On and Off
20
ANALOG INPUT BUFFERS OFF
18
ANALOG INPUT BUFFERS ON
16
14
12
10
8
6
4
2
0
0
2
4
6
8
10 12 14 16
FREQUENCY (MHz)
Figure 18. Noise vs. External Master Clock Frequency,
Analog Input Buffers On and Off
16800000
16780000
CONTINUOUS CONVERSION—REFERENCE DISABLED
STANDBY—REFERENCE DISABLED
STANDBY—REFERENCE ENABLED
16760000
16740000
16720000
16700000
16680000
16660000
1
10
100
1k
10k
SAMPLE NUMBER
Figure 19. Internal Reference Settling Time
AD7175-8
0
–20
–40
–60
–80
–100
–120
1
10
100
1k
10k
100k
1M
V_IN FREQUENCY (Hz)
Figure 20. Common-Mode Rejection Ratio (CMRR) vs. V_IN Frequency
(V_IN = 0.1 V, Output Data Rate = 250 kSPS)
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
–180
10
20
30
40
50
60
70
V_IN FREQUENCY (Hz)
Figure 21. Common-Mode Rejection Ratio (CMRR) vs. V_IN Frequency
(V_IN = 0.1 V, 10 Hz to 70 Hz, Output Data Rate = 20 SPS, Enhanced Filter)
–60
AVDD1—EXTERNAL 2.5V REFERENCE
AVDD1—INTERNAL 2.5V REFERENCE
–70
–80
–90
–100
–110
–120
–130
1
10 100 1k 10k 100k 1M 10M 100M
V_IN FREQUENCY (Hz)
Figure 22. Power Supply Rejection Ratio (PSRR) vs. V_IN Frequency
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