AD5334BRUZ Datasheet, PDF (13/20 Pages) Analog Devices – 2.5 V to 5.5 V, 500 mu
A, Parallel Interface

V_DD = 3V
V_DD = 5V
300 350 400 450 500 550 600
I_DD – ␮A
Figure 23. I_DD Histogram with V_DD =
3 V and V_DD = 5 V
AD5334/AD5335/AD5336/AD5344
0.929
0.928
0.927
0.926
0.925
0.924
0.923
0.922
0.921
0.920
0.919
500ns/DIV
Figure 24. AD5344 Major-Code Tran-
sition Glitch Energy
10
0
–10
–20
–30
–40
–50
–60
0.01 0.1 1 10 100 1k 10k
FREQUENCY – kHz
Figure 25. Multiplying Bandwidth
(Small-Signal Frequency Response)
0.4
V_DD = 5V
0.3 ^TA ^{= 25؇C}
0.2
0.1
0
–0.1
–0.2
0
1
2
3
4
5
6
V_REF – V
Figure 26. Full-Scale Error vs. V_REF
750ns/DIV
Figure 27. DAC-DAC Crosstalk
FUNCTIONAL DESCRIPTION
The AD5334/AD5335/AD5336/AD5344 are quad resistor-
string DACs fabricated on a CMOS process with resolutions of
8, 10, 10, and 12 bits, respectively. They are written to using a
parallel interface. They operate from single supplies of 2.5 V to
5.5 V and the output buffer amplifiers offer rail-to-rail output
swing. The gain of the buffer amplifiers in the AD5334 and
AD5336 can be set to 1 or 2 to give an output voltage range of
0 to V_REF or 0 to 2 V_REF. The AD5335 and AD5344 have out-
put buffers with unity gain.
The devices have a power-down feature that reduces current
consumption to only 80 nA @ 3 V.
Digital-to-Analog Section
The architecture of one DAC channel consists of a reference
buffer and a resistor-string DAC followed by an output buffer
amplifier. The voltage at the V_REF pin provides the reference
voltage for the DAC. Figure 28 shows a block diagram of the
DAC architecture. Since the input coding to the DAC is
straight binary, the ideal output voltage is given by:
V_OUT
= V_REF
×^D
2^N
× Gain
where:
D = decimal equivalent of the binary code which is loaded to
the DAC register:
0–255 for AD5334 (8 Bits)
0–1023 for AD5335/AD5336 (10 Bits)
0–4095 for AD5344 (12 Bits)
N = DAC resolution
Gain = Output Amplifier Gain (1 or 2)
V_REF
GAIN
INPUT
REGISTER
DAC
REGISTER
RESISTOR
STRING
V_OUT
OUTPUT
BUFFER AMPLIFIER
Figure 28. Single DAC Channel Architecture
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