5962-89710013A Datasheet, PDF (13/20 Pages) Analog Devices – CMOS Latched 8-/16-Channel Analog Multiplexers

TIMING
Figure 13 shows the timing sequence for latching the switch
address and enable inputs. The latches are level sensitive;
therefore, while WR is held low, the latches are transparent and
the switches respond to the address and enable inputs. This
input data is latched on the rising edge of WR.
ADG526A/ADG527A
Figure 14 shows the reset pulse width, tRS, and reset turn-off
time, tOFF (RS).
Note that all digital input signal rise and fall times are measured
from 10% to 90% of 3 V, tR = tF = 20 ns.
3V
WR
0V
3V
EN, A0, A1,
A2, (A3)
0V
1.5V
t_W
t_S
2.0V
t_H
0.8V
Figure 13. Timing Sequence
3V
RS
0V
V_O
SWITCH
OUTPUT
0V
1.5V
t_RS
t_OFF (RS)
0.8V
Figure 14. Reset Pulse
Rev. C | Page 13 of 20