ADV7282 Datasheet, PDF (12/32 Pages) Analog Devices – 10-Bit, 4 Oversampled SDTV Video Decoder with Differential Inputs and Deinterlacer

ADV7282
Data Sheet
DGND 1
D_VDDIO 2
D_VDD 3
DGND 4
INTRQ 5
GPO2 6
GPO1 7
GPO0 8
ADV7282-M
TOP VIEW
(Not to Scale)
24 A_IN4
23 A_IN3
22 DIAG1
21 A_VDD
20 VREFN
19 VREFP
18 A_IN2
17 A_IN1
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO DGND.
Figure 7. Pin Configuration, ADV7282-M
Table 10. Pin Function Descriptions, ADV7282-M
Pin No.
Mnemonic Type
Description
1, 4
DGND
Ground
Ground for Digital Supply.
2
DVDDIO
Power
Digital I/O Power Supply (3.3 V).
3
DVDD
Power
Digital Power Supply (1.8 V).
5
INTRQ
Output
Interrupt Request Output. An interrupt occurs when certain signals are detected on the
input video.
6 to 8
GPO2 to
GPO0
Output
General-Purpose Outputs. These pins can be configured via I²C to allow control of external
devices.
9
D0P
Output
Positive MIPI Differential Data Output.
10
D0N
Output
Negative MIPI Differential Data Output.
11
CLKP
Output
Positive MIPI Differential Clock Output.
12
CLKN
Output
Negative MIPI Differential Clock Output.
13
MVDD
Power
MIPI Digital Power Supply (1.8 V).
14
XTALP
Output
Connect this pin to the external 28.63636 MHz crystal, or leave it unconnected if an external
1.8 V, 28.63636 MHz clock oscillator source is used to clock the ADV7282-M. The crystal used
with the ADV7282-M must be a fundamental crystal.
15
XTALN
Input
Input Pin for the External 28.63636 MHz Crystal. The crystal used with the ADV7282-M must
be a fundamental crystal. If an external 1.8 V, 28.63636 MHz clock oscillator source is used to
clock the ADV7282-M, the output of the oscillator is fed into the XTALN pin.
16
17, 18, 23,
24, 26, 27
PVDD
AIN1 to AIN6
Power
Input
PLL Power Supply (1.8 V).
Analog Video Input Channels.
19
VREFP
Output
Internal Voltage Reference Output.
20
VREFN
Output
Internal Voltage Reference Output.
21
AVDD
Power
Analog Power Supply (1.8 V).
22
DIAG1
Input
Diagnostic Input 1.
25
DIAG2
Input
Diagnostic Input 2.
28
RESET
Input
System Reset Input (Active Low). A minimum low reset pulse width of 5 ms is required to
reset the ADV7282-M circuitry.
29
ALSB
Input
This pin selects the I²C write address for the ADV7282-M. When ALSB is set to Logic 0, the
write address is 0x40; when ALSB is set to Logic 1, the write address is 0x42.
30
SDATA
Input/output I²C Port Serial Data Input/Output.
31
SCLK
Input
I²C Port Serial Clock Input. The maximum clock rate is 400 kHz.
32
PWRDWN
Input
Power-Down Pin. A logic low on this pin places the ADV7282-M in power-down mode.
EPAD (EP)
Exposed Pad. The exposed pad must be connected to DGND.
Rev. A | Page 12 of 32