AD9516-2_15 Datasheet, PDF (12/80 Pages) Analog Devices – 14-Output Clock Generator with Integrated 2.2 GHz VCO

AD9516-2
Data Sheet
DELAY BLOCK ADDITIVE TIME JITTER
Table 13.
Parameter
DELAY BLOCK ADDITIVE TIME JITTER¹
100 MHz Output
Delay (1600 µA, 0x1C) Fine Adj. 000000
Delay (1600 µA, 0x1C) Fine Adj. 101111
Delay (800 µA, 0x1C) Fine Adj. 000000
Delay (800 µA, 0x1C) Fine Adj. 101111
Delay (800 µA, 0x4C) Fine Adj. 000000
Delay (800 µA, 0x4C) Fine Adj. 101111
Delay (400 µA, 0x4C) Fine Adj. 000000
Delay (400 µA, 0x4C) Fine Adj. 101111
Delay (200 µA, 0x1C) Fine Adj. 000000
Delay (200 µA, 0x1C) Fine Adj. 101111
Delay (200 µA, 0x4C) Fine Adj. 000000
Delay (200 µA, 0x4C) Fine Adj. 101111
Min Typ Max Unit
Test Conditions/Comments
Incremental additive jitter
0.54
ps rms
0.60
ps rms
0.65
ps rms
0.85
ps rms
0.79
ps rms
1.2
ps rms
1.2
ps rms
2.0
ps rms
1.3
ps rms
2.5
ps rms
1.9
ps rms
3.8
ps rms
1 _{This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter}
should be added to this value using the root sum of the squares (RSS) method.
SERIAL CONTROL PORT
Table 14.
Parameter
CS (INPUT)
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
SCLK (INPUT)
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
SDIO (WHEN INPUT)
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
SDIO, SDO (OUTPUTS)
Output Logic 1 Voltage
Output Logic 0 Voltage
TIMING
Clock Rate (SCLK, 1/tSCLK)
Pulse Width High, tHIGH
Pulse Width Low, tLOW
SDIO to SCLK Setup, tDS
SCLK to SDIO Hold, tDH
SCLK to Valid SDIO and SDO, tDV
CS to SCLK Setup and Hold, tS, tH
CS Minimum Pulse Width High, tPWH
Min Typ Max Unit
2.0
V
0.8 V
3
µA
110
µA
2
pF
2.0
V
0.8 V
110
µA
1
µA
2
pF
2.0
V
0.8 V
10
nA
20
nA
2
pF
2.7
V
0.4 V
25
MHz
16
ns
16
ns
2
ns
1.1
ns
8
ns
2
ns
3
ns
Rev. C | Page 12 of 80
Test Conditions/Comments
CS has an internal 30 kΩ pull-up resistor
SCLK has an internal 30 kΩ pull-down resistor