AD8183 Datasheet, PDF (12/16 Pages) Analog Devices – 380 MHz, 25 mA, Triple 2:1 Multiplexers

AD8183/AD8185
result, the input and output traces, in addition to having a con-
trolled impedance, are well shielded.
SEL A/B AND OE
SEL A/B (Pin 22 of the device) allows the A or B inputs to be
selected.
When SEL A/B is at logic low, (equal to or less than 0.8 V),
inputs 0A, 1A and 2A are directed to OUTPUTs 0, 1, and 2,
respectively. When SEL A/B is at logic high, (equal to or greater
than 2.0 V), inputs 0B, 1B, and 2B are directed to OUTPUTs
0, 1, and 2, respectively.
There are two ways to provide SEL A/B to the device: using a
jumper or a BNC connection. With the jumper in the W4 posi-
tion, SEL A/B is tied to ground. This selects the A inputs.
With the jumper in the W3 position, SEL A/B is tied to 5 V,
through pull up resistor R15. This selects the B inputs.
If faster use of SEL A/B is desired, the 50 Ω BNC connector at
J10 can be used. If J10 is used, there must NOT be a jumper on
W3 and W4. Microstrip line techniques provide a 50 Ω charac-
teristic impedance from J10 to the device. Please refer to Figure
41 for the arrangement of the PCB layers. If J10 is used, the
user may wish to install a 50 Ω termination resistor at R10.
OE (Pin 23 of the device) allows the three outputs to be enabled
or disabled. When OE is at logic low, (equal to or less than
0.8 V), Outputs 0, 1, and 2 are enabled. When OE is at logic
high, (equal to or greater than 2.0 V), Outputs 0, 1, and 2 are
disabled (placed into a high impedance state).
Once again, there are two different ways to provide OE to the
device: using a jumper or a BNC connection. With the jumper
in the W2 position, OE is tied to ground. This enables the outputs.
With the jumper in the W1 position, OE is tied to 5 V, through
pull-up resistor R16. This selects “Hi Z,” or high impedance,
and the outputs are disabled.
If faster use of OE is desired, the 50 Ω BNC connector at J11
can be used. If J11 is used, there must NOT be a jumper on W1
and W2. Microstrip line techniques provide a 50 Ω characteris-
tic impedance from J11 to the device. Please refer to Figure 41
for the arrangement of the PCB layers. If J11 is used, the user
may wish to install a 50 Ω termination resistor at R11.
DVCC
DVCC P1 1
+ _C3
10␮F
DGND
DGND
C6
0.1␮F
DGND
DVCC
DGND P1 2
VEE
DGND
VEE P1 4
C2
+ 10␮F
VEE
C5
0.1␮F
AGND
AGND
AGND
AGND P1 5
VCC
AGND
VCC
R16
20k⍀
W1
OE
W2
VCC P1 6
+ _C1
10␮F
AGND
VCC
C4
0.1␮F
AGND
VCC
R15
20k⍀
W3
W4
SEL A/B
OE J11
IN0A J1
R1
75⍀
75⍀ STRIPLINE
IN1A J2
AGND
R2
75⍀
75⍀ STRIPLINE
IN2A J3
IN2B J4
AGND
R3
75⍀
AGND
R4
75⍀
75⍀ STRIPLINE
VCC
VEE
C7
0.01␮F
AGND
75⍀ STRIPLINE
C8
0.01␮F
AGND
IN1B J5
AGND
R5
75⍀
75⍀ STRIPLINE
IN0B J6
AGND
R6
75⍀
75⍀ STRIPLINE
AGND
DGND
50⍀ MICROSTRIP LINE
R11
50⍀
OPTIONAL
DGND
VCC
C15
0.01␮F
AGND
DGND
AGND
AGND
AGND
DUT
1 _IN0A
VCC ²⁴
2
DGND
OE ²³
3
IN1A
SEL A/B ²²
4 _AGND
5 _IN2A
21
VCC
20
OUT0
6 _{VCC AD8183/ VEE} 19
7 _VEE AD8185 _OUT1 18
8 _IN2B
VCC ¹⁷
9 _AGND
OUT2 ¹⁶
10 _IN1B
11 _AGND
VEE ¹⁵
DVCC ¹⁴
12 _IN0B
VCC ¹³
W5
C9
0.01␮F
AGND
50⍀ MICROSTRIP LINE
R10
50⍀
OPTIONAL
DGND
VCC
C14
0.01␮F
AGND
R14
75⍀
C13
0.01␮F
AGND
VEE
R13
75⍀
C10
0.01␮F
DGND
C12
0.01␮F
AGND
VCC
R12
75⍀
C11
0.01␮F
AGND
VEE
DVCC
VCC
DGND
75⍀ STRIPLINE
75⍀ STRIPLINE
75⍀ STRIPLINE
AGND
DGND
Figure 42.␣ Evaluation Board Schematic
–12–
J10 SEL A/B
J9 OUT0
J8 OUT1
J7 OUT2
REV. 0