ADSP-21992_15 Datasheet, PDF (11/60 Pages) Analog Devices – Mixed-Signal DSP Controller with CAN

The encoder interface unit incorporates programmable noise
filtering on the four encoder inputs to prevent spurious noise
pulses from adversely affecting the operation of the quadrature
counter. The encoder interface unit operates at a clock fre-
quency equal to the HCLK rate. The encoder interface unit
operates correctly with encoder signals at frequencies of up to
13.25 MHz, at the 80 MHz HCLK rate, corresponding to a max-
imum quadrature frequency of 53 MHz (assuming an ideal
quadrature relationship between the input EIA and EIB signals).
The EIU may be programmed to use the north marker on EIZ to
reset the quadrature encoder in hardware, if required.
Alternatively, the north marker can be ignored, and the encoder
quadrature counter is reset according to the contents of a maxi-
mum count register, EIUMAXCNT. There is also a “single
north marker” mode available in which the encoder quadrature
counter is reset only on the first north marker pulse.
The encoder interface unit can also be made to implement some
error checking functions. If an encoder count error is detected
(due to a disconnected encoder line, for example), a status bit in
the EIUSTAT register is set, and an EIU count error interrupt is
generated.
The encoder interface unit of the ADSP-21992 contains a 16-bit
loop timer that consists of a timer register, period register, and
scale register so that it can be programmed to time out and
reload at appropriate intervals. When this loop timer times out,
an EIU loop timer timeout interrupt is generated. This interrupt
could be used to control the timing of speed and position con-
trol loops in high performance drives.
The encoder interface unit also includes a high performance
encoder event timer (EET) block that permits the accurate tim-
ing of successive events of the encoder inputs. The EET can be
programmed to time the duration between up to 255 encoder
pulses and can be used to enhance velocity estimation, particu-
larly at low speeds of rotation.
FLAG I/O (FIO) PERIPHERAL UNIT
The FIO module is a generic parallel I/O interface that supports
16 bidirectional multifunction flags or general-purpose digital
I/O signals (PF15–PF0).
All 16 FLAG bits can be individually configured as an input or
output based on the content of the direction (DIR) register, and
can also be used as an interrupt source for one of two FIO inter-
rupts. When configured as input, the input signal can be
programmed to set the FLAG on either a level (level sensitive
input/interrupt) or an edge (edge sensitive input/interrupt).
The FIO module can also be used to generate an asynchronous
unregistered wake-up signal FIO_WAKEUP for DSP core wake
up after power-down.
The FIO lines, PF7–PF1 can also be configured as external slave
select outputs for the SPI communications port, while PF0 can
be configured to act as a slave select input.
The FIO lines can be configured to act as a PWM shutdown
source for the 3-phase PWM generation unit of the
ADSP-21992.
ADSP-21992
WATCHDOG TIMER
The ADSP-21992 integrates a watchdog timer that can be used
as a protection mechanism against unintentional software
events. It can be used to cause a complete DSP and peripheral
reset in such an event. The watchdog timer consists of a 16-bit
timer that is clocked at the external clock rate (CLKIN or crystal
input frequency).
In order to prevent an unwanted timeout or reset, it is necessary
to periodically write to the watchdog timer register. During
abnormal system operation, the watchdog count will eventually
decrement to 0 and a watchdog timeout will occur. In the sys-
tem, the watchdog timeout will cause a full reset of the DSP core
and peripherals.
GENERAL-PURPOSE TIMERS
The ADSP-21992 contains a general-purpose timer unit that
contains three identical 32-bit timers. The three programmable
interval timers (Timer0, Timer1, and Timer2) generate periodic
interrupts. Each timer can be independently set to operate in
one of three modes:
• Pulse waveform generation (PWM_OUT) mode.
• Pulse width count/capture (WDTH_CAP) mode.
• External event watchdog (EXT_CLK) mode.
Each Timer has one bidirectional chip pin, TMR2-TMR0. For
each timer, the associated pin is configured as an output pin in
PWM_OUT mode and as an input pin in WDTH_CAP and
EXT_CLK modes.
INTERRUPTS
The interrupt controller lets the DSP respond to 17 interrupts
with minimum overhead. The DSP core implements an inter-
rupt priority scheme as shown in Table 2. Applications can use
the unassigned slots for software and peripheral interrupts. The
peripheral interrupt controller is used to assign the various
peripheral interrupts to the 12 user assignable interrupts of the
DSP core.
Table 2. Interrupt Priorities/Addresses
Interrupt
Emulator (NMI)
—Highest Priority
Reset (NMI)
IMASK/
IRPTL
NA
Vector Address
NA
0
0x00 0000
Power-Down (NMI)
Loop and PC Stack
Emulation Kernel
1
0x00 0020
2
0x00 0040
3
0x00 0060
User Assigned Interrupt
4
(USR0)
0x00 0080
Rev. A | Page 11 of 60 | August 2007