ADSP-21992_15 Datasheet, PDF (1/60 Pages) Analog Devices – Mixed-Signal DSP Controller with CAN

Mixed-Signal DSP Controller with CAN
ADSP-21992
FEATURES
ADSP-2199x, 16-bit, fixed-point DSP core with up to 160
MIPS sustained performance
48K words of on-chip RAM, as 32K words on-chip 24-bit pro-
gram RAM, and 16K words on-chip, 16-bit data RAM
External memory interface
Dedicated memory DMA controller for data/instruction
transfer between internal/external memory
Programmable PLL and flexible clock generation circuitry
enables full-speed operation from low speed
input clocks
IEEE JTAG Standard 1149.1 test access port supports on-chip
emulation and system debugging
8-channel, 14-bit analog-to-digital converter system, with up
to 20 MSPS sampling rate (at 160 MHz core clock rate)
3-phase 16-bit center based PWM generation unit with 12.5
ns resolution at 160 MHz core clock (CCLK) rate
Dedicated 32-bit encoder interface unit with companion
encoder event timer
Dual 16-bit auxiliary PWM outputs
16 general-purpose flag I/O pins
3 programmable 32-bit interval timers
SPI communications port with master or slave operation
Synchronous serial communications port (SPORT) capable of
software UART emulation
Controller area network (CAN) module, fully compliant with
V2.0B standard
Integrated watchdog timer
Dedicated peripheral interrupt controller with software
priority control
Multiple boot modes
Precision 1.0 V voltage reference
Integrated power-on-reset (POR) generator
Flexible power management with selectable power-down
and idle modes
2.5 V internal operation with 3.3 V I/O
Operating temperature ranges of –40ЊC to +85ЊC and –40ЊC
to +125ЊC
CLOCK
GENERATOR/PLL
JTAG
TEST AND
EMULATION
ADSP-219x
DSP CORE
I/O
BUS
I/O REGISTERS
32K Ï« 24
PM RAM
16K Ï« 16
DM RAM
4K Ï« 24
PM ROM
PM ADDRESS/DATA
DM ADDRESS/DATA
SPI
EXTERNAL
MEMORY
INTERFACE
(EMI)
ADDRESS
DATA
CONTROL
SPORT
CONTROLLER AREA
NETWORK (CAN)
MEMORY DMA
CONTROLLER
PWM
GENERATION
UNIT
ENCODER
INTERFACE
UNIT
(AND EET)
AUXILIARY
PWM
UNIT
TIMER 0
TIMER 1
TIMER 2
FLAG
I/O
WATCHDOG
TIMER
INTERRUPT
CONTROLLER
(ICNTL)
ADC
CONTROL
POR
PIPELINE
FLASH ADC
VREF
Figure 1. Functional Block Diagram
Rev. A
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