ADSP-2188M Datasheet, PDF (11/52 Pages) Analog Devices – DSP Microcomputer

ADSP-2188M Preliminary Data Sheet
For current information contact Analog Devices at [phone]
April 1999
Slow Idle
The IDLE instruction is enhanced on the ADSP-2188M to let the processor’s internal clock signal be
slowed, further reducing power consumption. The reduced clock frequency, a programmable fraction
of the normal clock rate, is specified by a selectable divisor given in the IDLE instruction.
The format of the instruction is:
IDLE (n);
where n = 16, 32, 64, or 128. This instruction keeps the processor fully functional, but operating at the
slower clock rate. While it is in this state, the processor’s other internal clock signals, such as SCLK,
CLKOUT, and timer clock, are reduced by the same ratio. The default form of the instruction, when
no clock divisor is given, is the standard IDLE instruction.
When the IDLE (n) instruction is used, it effectively slows down the processor’s internal clock and thus
its response time to incoming interrupts. The one-cycle response time of the standard idle state is
increased by n, the clock divisor. When an enabled interrupt is received, the ADSP-2188M will remain
in the idle state for up to a maximum of n processor cycles (n = 16, 32, 64, or 128) before resuming
normal operation.
When the IDLE (n) instruction is used in systems that have an externally generated serial clock (SCLK),
the serial clock rate may be faster than the processor’s reduced internal clock rate. Under these
conditions, interrupts must not be generated at a faster rate than can be serviced, due to the additional
time the processor takes to come out of the idle state (a maximum of n processor cycles).
SYSTEM INTERFACE
Figure 2 shows typical basic system configurations with the ADSP-2188M, two serial devices, a byte-
wide EPROM, and optional external program and data overlay memories (mode selectable).
Programmable wait state generation allows the processor connects easily to slow peripheral devices. The
ADSP-2188M also provides four external interrupts and two serial ports or six external interrupts and
one serial port. Host Memory Mode allows access to the full external data bus, but limits addressing to
REV. PrA
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
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