ADSP-2188M Datasheet, PDF (1/52 Pages) Analog Devices – DSP Microcomputer

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Preliminary Technical Data
DSP
Microcomputer
ADSP-2188M
FEATURES
Performance
• ^{12.5 ns Instruction Cycle Time @ 2.5 Volts (internal), 75 MIPS Sustained Performance}
• ^{Single-Cycle Instruction Execution}
• ^{Single-Cycle Context Switch}
• ^{3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle}
• ^{Multifunction Instructions}
• ^{Powerdown Mode Featuring Low CMOS Standby Power Dissipation with 200 CLKIN Cycle Recovery from}
Powerdown Condition
Y • ^{Low Power Dissipation in Idle Mode}
R _Integration
A _{• ADSP-2100 Family Code Compatible (easy to use algebraic syntax), with Instruction Set Extensions}
I ^{N • 256K Bytes of On-Chip RAM, Configured as 48K Words On-Chip Program Memory RAM and 56K Words}
L On-Chip Data Memory RAM
I ^{M A • Dual Purpose Program Memory for Both Instruction and Data Storage}
L I ^{C • Independent ALU, Multiplier/Accumulator, & Barrel Shifter Computational Units}
• ^{Two Independent Data Address Generators}
E _{N • Powerful Program Sequencer Provides Zero Overhead Looping Conditional Instruction Execution}
P ^{R H A • Programmable 16-Bit Interval Timer with Prescaler}
C _T • ^{100-Lead LQFP}
T ^{E A System Interface}
D _• Flexible I/O structure allows 2.5V or 3.3V operation; all inputs tolerate up to 3.6V regardless of mode
• ^{16-Bit Internal DMA Port for High Speed Access to on-Chip Memory (Mode Selectable)}
• ^{4 MByte Memory Interface for Storage of Data Tables & Program Overlays (Mode Selectable)}
• ^{8-Bit DMA to Byte Memory for Transparent Program and Data Memory Transfers (Mode Selectable)}
• ^{I/O Memory Interface with 2048 Locations Supports Parallel Peripherals (Mode Selectable)}
• ^{Programmable Memory Strobe & Separate I/O Memory Space Permits “Glueless” System Design}
• ^{Programmable Wait State Generation}
• ^{Two Double-Buffered Serial Ports with Companding Hardware and Automatic Data Buffering}
• ^{Automatic Booting of On-Chip Program Memory from Byte-Wide External Memory, e.g., EPROM, or}
Through Internal DMA Port
• ^{Six External Interrupts}
• ^{13 Programmable Flag Pins Provide Flexible System Signaling}
• ^{UART Emulation through Software SPORT Reconfiguration}
• ^{ICE-Port™ Emulator Interface Supports Debugging in Final Systems}
REV. PrA
This information applies to a product under development. Its characteristics and
specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacturing unless otherwise agreed to in writing.
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©Analog Devices Inc., 1999