AD9995_15 Datasheet, PDF (11/60 Pages) Analog Devices – 12-Bit CCD Signal Processor with Precision Timing Generator

AD9995
mapped into four quadrants, with each quadrant containing 12
Digital Data Outputs
edge locations. Table II shows the correct register values for the
The AD9995 data output and DCLK phases are programmable
corresponding edge locations.
using the DOUTPHASE register (Addr. 0x37, Bits [5:0]). Any
Figure 7 shows the default timing locations for all of the high
speed clock signals.
edge from 0 to 47 may be programmed, as shown in Figure 8a.
Normally, the DOUT and DCLK signals will track in phase
based on the DOUTPHASE register contents. The DCLK
H-Driver and RG Outputs
output phase can also be held fixed with respect to the data out-
In addition to the programmable timing positions, the AD9995
puts by changing the DCLKMODE register high (Addr. 0x37,
features on-chip output drivers for the RG and H1–H4 outputs.
Bit 6). In this mode, the DCLK output will remain at a fixed
These drivers are powerful enough to directly drive the CCD
phase equal to CLO (the inverse of CLI) while the data output
inputs. The H-driver and RG current can be adjusted for optimum _{phase is still programmable.}
rise/fall time into a particular load by using the DRVCONTROL
register (Addr. 0x35). The 3-bit drive setting for each output is
There is a fixed output delay from the DCLK rising edge to the
adjustable in 4.1 mA increments, with the minimum setting of 0
equal to OFF or three-state, and the maximum setting of 7 equal
to 30.1 mA.
As shown in Figures 5, 6, and 7, the H2 and H4 outputs are
inverses of H1 and H3, respectively. The H1/H2 crossover volt-
age is approximately 50% of the output swing. The crossover
E _{voltage is not programmable.}
DOUT transition, called t_OD. This delay can be programmed to
four values between 0 ns and 12 ns by using the DOUTDELAY
register (Addr. 0x037, Bits [8:7]). The default value is 8 ns.
The pipeline delay through the AD9995 is shown in Figure 8b.
After the CCD input is sampled by SHD, there is an 11-cycle
delay until the data is available.
T _Parameter
Polarity
Positive Edge
E _{Negative Edge}
Sampling Location
Drive Strength
Table I. Timing Core Register Parameters for H1, H3, RG, SHP/SHD
Length
Range
Description
1b
High/Low
Polarity Control for H1, H3, and RG (0 = No Inversion, 1 = Inversion)
6b
0–47 Edge Location Positive Edge Location for H1, H3, and RG
6b
0–47 Edge Location Negative Edge Location for H1, H3, and RG
6b
0–47 Edge Location Sampling Location for Internal SHP and SHD Signals
3b
0–47 Current Steps Drive Current for H1–H4 and RG Outputs (4.1 mA per Step)
L _CCD
SIGNAL
O _RG
S _H1/H3
H2/H4
B _{USING THE SAME TOGGLE POSITIONS FOR H1 AND H3 GENERATES STANDARD 2-PHASE H-CLOCKING.}
O ^{Figure 6. 2-Phase H-Clock Operation}
Quadrant
I
II
III
IV
Table II. Precision Timing Edge Locations
Edge Location (Dec)
Register Value (Dec)
0 to 11
12 to 23
24 to 35
36 to 47
0 to 11
16 to 27
32 to 43
48 to 59
Register Value (Bin)
000000 to 001011
010000 to 011011
100000 to 101011
110000 to 111011
REV. 0
–11–