AD9831ASTZ Datasheet, PDF (11/16 Pages) Analog Devices – DIRECT DIGITAL SYNTGESIZER WAVEFORM GENERATOR

AD9831
DSP and MPU Interfacing
The AD9831 has a parallel interface, with 16 bits of data being
loaded during each write cycle.
The frequency or phase registers are loaded by asserting the WR
signal. The destination register for the 16 bit data is selected
using the address inputs A0, A1 and A2. The phase registers
are 12 bits wide so, only the 12 LSBs need to be valid—the
4 MSBs of the 16 bit word do not have to contain valid data.
Data is loaded into the AD9831 by pulsing WR low, the data
being latched into the AD9831 on the rising edge of WR. The
values of inputs A0, A1 and A2 are also latched into the
AD9831 on the WR rising edge. The appropriate destination
register is updated on the next MCLK rising edge. If the WR
rising edge coincides with the MCLK rising edge, there is an
uncertainty of one MCLK cycle regarding the loading of the
destination register—the destination register may be loaded
immediately or the destination register may be updated on the
next MCLK rising edge. To avoid any uncertainty, the times
listed in the specifications should be complied with.
FSELECT, PSEL0 and PSEL1 are sampled on the MCLK
rising edge. Again, these inputs should be valid when an
MCLK rising edge occurs as there will be an uncertainty of one
MCLK cycle introduced otherwise. When these inputs change
value, there will be a pipeline delay before control is transferred
to the selected register—there will be a pipeline delay before the
analog output is controlled by the selected register. There is a
similar delay when a new word is written to a register. PSEL0,
PSEL1, FSELECT and WR have latencies of six MCLK cycles.
The flow chart in Figure 22 shows the operating routine for the
AD9831. When the AD9831 is powered up, the part should be
reset using RESET. This will reset the phase accumulator to
zero so that the analog output is at midscale. RESET does not
reset the phase and frequency registers. These registers will
contain invalid data and, therefore, should be set to zero by the
user.
The registers to be used should be loaded, the analog output
being f_MCLK/2³² × FREG where FREG is the value loaded into
the selected frequency register. This signal will be phase shifted
by the amount specified in the selected phase register (2π/4096
× PHASEREG where PHASEREG is the value contained in the
selected phase register). When FSELECT, PSEL0 and PSEL1
are programmed, there will be a pipeline delay of approximately
6 MCLK cycles before the analog output reacts to the change
on these inputs.
RESET
DATA WRITE
FREG<0, 1> = 0
PHASEREG<0, 1, 2, 3> = 0
DATA WRITE
FREG<0> = f_OUT0/f_MCLK*2³²
FREG<1> = f_OUT1/f_MCLK*2³²
PHASEREG<3:0> = DELTA PHASE<0, 1, 2, 3>
SELECT DATA SOURCES
SET FSELECT
SET PSEL0, PSEL1
WAIT 6 MCLK CYCLES
DAC OUTPUT
V_OUT = V_REFIN*6.25*R_OUT/R_SET*(1 + SIN(2π(FREG*f_MCLK*t/2³² + PHASEREG/2¹²)))
CHANGE FSELECT
YES
CHANGE PHASE?
NO
NO
CHANGE F_OUT?
YES
NO
CHANGE FREG?
NO
CHANGE PHASEREG?
YES
YES
CHANGE PSEL0, PSEL1
Figure 22. Flow Chart for AD9831 Initialization and Operation
REV. B
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