AD5665_15 Datasheet, PDF (11/36 Pages) Analog Devices – Quad, 12-/14-/16-Bit nanoDACs with 5 ppm/C On-Chip Reference, IC Interface

Data Sheet
AD5625R/AD5645R/AD5665R, AD5625/AD5665
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
LDAC 1
ADDR1 2
V_DD 3
V_OUTA 4
V_OUTC 5
POR 6
V_REFIN/V_REFOUT 7
AD5625R/
AD5645R/
AD5665R
TOP VIEW
(Not to Scale)
14 SCL
13 SDA
12 GND
11 V_OUTB
10 V_OUTD
9 CLR
8 ADDR2
V_OUTA 1
V_OUTB 2
GND 3
V_OUTC 4
V_OUTD 5
AD5625R/
AD5645R/
AD5665R
TOP VIEW
(Not to Scale)
10 V_REFIN/V_REFOUT
9 V_DD
8 SDA
7 SCL
6 ADDR
EXPOSED PAD TIED TO GND.
Figure 4. Pin Configuration (14-Lead TSSOP), R Suffix Version
Figure 6. Pin Configuration (10-Lead LFCSP), R Suffix Version
LDAC 1
ADDR1 2
V_DD 3
V_OUTA 4
V_OUTC 5
POR 6
V_REFIN 7
AD5625/
AD5665
TOP VIEW
(Not to Scale)
14 SCL
13 SDA
12 GND
11 V_OUTB
10 V_OUTD
9 CLR
8 ADDR2
Figure 5. Pin Configuration (14-Lead TSSOP)
V_OUTA 1
V_OUTB 2
GND 3
V_OUTC 4
V_OUTD 5
AD5625/
AD5665
TOP VIEW
(Not to Scale)
10 V_REFIN
9 V_DD
8 SDA
7 SCL
6 ADDR
EXPOSED PAD TIED TO GND.
Figure 7. Pin Configuration (10-Lead LFCSP)
Table 7. Pin Function Descriptions
Pin Number
14-Lead 10-Lead Mnemonic Description
1
N/A
LDAC
Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data.
This allows simultaneous update of all DAC outputs. Alternatively, this pin can be tied permanently
low.
2
N/A
ADDR1
Three-State Address Input. Sets the two least significant bits (Bit A1, Bit A0) of the 7-bit slave address
(see Table 10).
3
9
VDD
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be
decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
4
1
VOUTA
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
5
4
VOUTC
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
6
N/A
POR
Power-On Reset Pin. Tying the POR pin to GND powers up the part to 0 V. Tying the POR pin to VDD
powers up the part to midscale.
7
10
VREFIN/VREFOUT The AD56x5R have a common pin for reference input and reference output. When using the internal
reference, this is the reference output pin. When using an external reference, this is the reference
input pin. The default for this pin is as a reference input. (The internal reference and reference output
are only available on R suffix versions.) The AD56x5 has a reference input pin only.
8
N/A
ADDR2
Three-State Address Input. Sets Bit A3 and Bit A2 of the 7-bit slave address (see Table 10).
9
N/A
CLR
Asynchronous Clear Input. The CLR input is falling-edge sensitive. While CLR is low, all LDAC pulses
are ignored. When CLR is activated, zero scale is loaded to all input and DAC registers. This clears the
output to 0 V. The part exits clear code mode on the falling edge of the ninth clock pulse of the last
byte of the valid write. If CLR is activated during a write sequence, the write is aborted. If CLR is
activated during high speed mode, the part exits high speed mode.
10
5
VOUTD
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
11
2
VOUTB
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
12
3
GND
Ground Reference Point for All Circuitry on the Part.
13
8
SDA
Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the 16-bit
input register. It is a bidirectional, open-drain data line that should be pulled to the supply with an
external pull-up resistor.
14
7
SCL
Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 16-bit
input register.
N/A
6
ADDR
Three-State Address Input. Sets the two least significant bits (Bit A1, Bit A0) of the 7-bit slave address
(see Table 9).
EPAD
For the 10-lead LFCSP, the exposed pad must be tied to GND.
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