ADUC7034 Datasheet, PDF (102/142 Pages) Analog Devices – Integrated Precision Battery Sensor for Automotive

ADuC7034
Preliminary Technical Data
High Voltage Configuration0 Register
Name:
HVCFG0
Address:
Indirectly addressed via the HVCON high voltage interface
Default Value: 0x00
Access:
Read/write
Function:
This 8-bit register controls the function of high voltage circuits on the ADuC7034. This register is not an MMR and
does not appear in the MMR memory map. It is accessed via the HVCON registered interface. Data to be written to
this register is loaded via the HVDAT MMR, and data is read back from this register via the HVDAT MMR.
Table 73. HVCFG0 Bit Designations
Bit
Description
7
Wake/STI Thermal Shutdown Disable.
This bit is set to 1 to disable the automatic shutdown of the wake/STI driver when a thermal event occurs.
This bit is cleared to 0 to enable the automatic shutdown of the wake/STI driver when a thermal event occurs.
6
Precision Oscillator Enable Bit.
This bit is set to 1 to enable the precision, 131 kHz oscillator. The oscillator start-up time is typically 70 µs (including
high voltage interface latency of 10 µs).
This bit is cleared to 0 to power down the precision, 131 kHz oscillator.
5
Bit Serial Device (BSD) Mode Enable Bit.
This bit is cleared to 0 to enable an internal (LIN) pull-up resistor on the LIN/BSD pin.
This bit is set to 1 to disable the internal (LIN) pull-up and configure the LIN/BSD pin for BSD operation.
4
Wake Up (WU) Assert Bit.
This bit is set to 1 to assert the external WU pin high.
This bit is cleared to 0 to pull the external WU pin low via an internal 10 kΩ pull-down resistor.
3
Power Supply Monitor (PSM) Enable Bit.
This bit is cleared to 0 to disable the power supply (voltage at the VDD pin) monitor.
This bit is set to 1 to enable the power supply (voltage at the VDD pin) monitor. If IRQ3 (IRQEN[16] is enabled the
PSM generates an interrupt if the voltage at the VDD pin drops below 6.0 V.
2
Low Voltage Flag (LVF) Enable Bit.
This bit is cleared to 0 to disable the LVF function.
This bit is set to 1 to enable the LVF function. The low voltage flag can be interrogated via HVMON[3] after power up
to determine if the REG_DVDD voltage previously dropped below 2.1 V.
1 to 0
LIN Operating Mode. These bits enable/disable the LIN driver.
00 = LIN disabled.
01 = reserved (not LIN V2.0 compliant).
10 = LIN enabled.
11 = reserved, not used.
Rev. Pr.A | Page 102 of 142