ADE5166_09 Datasheet, PDF (102/156 Pages) Analog Devices – Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver

ADE5166/ADE5169/ADE5566/ADE5569
Table 99. LCD Pointer SFR (LCDPTR, Address 0xAC)
Bit
Mnemonic
Default Description
7
R/W
0
Read or write LCD bit. If this bit is set to 1, the data in the LCD data SFR (LCDDAT, Address 0xAE)
is written to the address indicated by the ADDRESS bits (LCDPTR[3:0]).
6
Reserved
0
Reserved.
[5:4]
RAM2SCREEN 0
These bits select the screen recipient of the data memory action.
[3:0]
ADDRESS
0
LCD memory address (see Table 102).
Table 100. LCD Data SFR (LCDDAT, Address 0xAE)
Bit
Mnemonic
Default
Description
[7:0]
LCDDATA
0
Data to be written into or read out of the LCD memory SFRs.
Table 101. LCD Segment Enable 2 SFR (LCDSEGE2, Address 0xED)
Bit
Mnemonic
Default Description
[7:4]
Reserved
0
Reserved.
3
FP19EN
0
FP19 function select bit. 0 = general-purpose I/O, 1 = LCD function.
2
FP18EN
0
FP18 function select bit. 0 = general-purpose I/O, 1 = LCD function.
1
FP17EN
0
FP17 function select bit. 0 = general-purpose I/O, 1 = LCD function.
0
FP16EN
0
FP16 function select bit. 0 = general-purpose I/O, 1 = LCD function.
LCD SETUP
The LCD configuration SFR (LCDCON, Address 0x95) configures
the LCD module to drive the type of LCD in the user end system.
The BIAS bit (Bit 2) and the LMUX bits (Bits[1:0]) in this SFR
should be set according to the LCD specifications.
The COM2/FP28 and COM3/FP27 pins default to LCD segment
lines. Selecting the 3× multiplex level in the LCD configuration
SFR (LCDCON, Address 0x95) by setting LMUX[1:0] to 10
changes the FP28 pin functionality to COM2. The 4× multiplex
level selection, LMUX[1:0] = 11, changes the FP28 pin function-
ality to COM2 and the FP27 pin functionality to COM3.
The LCD segments of FP0 to FP15 are enabled by default. Addi-
tional pins are selected for LCD functionality in the LCD segment
enable SFR (LCDSEGE, Address 0x97) and LCD Segment Enable 2
SFR (LCDSEGE2, Address 0xED), where there are individual
enable bits for the FP16 to FP25 segment pins. The LCD pins do
not need to be enabled sequentially. For example, if the Timer 2
input, which is the alternate function of FP23, is required, any of
the other shared pins, FP16 to FP25 for the ADE5166/ADE5169
and FP16 to F26 for the ADE5566/ADE5569, can be enabled
instead.
The Display Element Control section contains details about
setting up the LCD data memory to turn individual LCD
segments on and off. Setting the LCDRST bit (Bit 6) in the LCD
configuration SFR (LCDCON, Address 0x95) resets the LCD
data memory to its default (0). A power-on reset also clears the
LCD data memory.
LCD TIMING AND WAVEFORMS
An LCD segment acts like a capacitor that is charged and dis-
charged at a certain rate. This rate, the refresh rate, determines
the visual characteristics of the LCD. A slow refresh rate results
in the LCD blinking on and off between refreshes. A fast refresh
rate presents a screen that appears to be continuously lit. In
addition, a faster refresh rate consumes more power.
The frame rate, or refresh rate, for the LCD module is derived
from the LCD clock, fLCDCLK. The LCD clock is selected as 2048 Hz
or 128 Hz by the CLKSEL bit (Bit 3) in the LCD configuration
SFR (LCDCON, Address 0x95). The minimum refresh rate needed
for the LCD to appear solid (without blinking) is independent of
the multiplex level.
The LCD waveform frequency, fLCD, is the frequency at which the
LCD switches the active common line. Thus, the LCD waveform
frequency depends heavily on the multiplex level. The frame rate
and LCD waveform frequency are set by fLCDCLK, the multiplex
level, and the FD frame rate selection bits in the LCD clock SFR
(LCDCLK, Address 0x96[3:0]).
The LCD module provides 16 different frame rates for fLCDCLK =
2048 Hz, ranging from 8 Hz to 128 Hz for an LCD with 4×
multiplexing. Fewer options are available with fLCDCLK = 128 Hz,
ranging from 8 Hz to 32 Hz for a 4× multiplexed LCD. The
128 Hz clock is beneficial for battery operation because it consumes
less power than the 2048 Hz clock. The frame rate is set by the
FD bits in the LCD clock SFR (LCDCLK, Address 0x96[3:0]);
see Table 96 and Table 97.
The LCD waveform is inverted at twice the LCD waveform fre-
quency, fLCD. This way, each frame has an average dc offset of 0.
ADC offset degrades the lifetime and performance of the LCD.
Rev. B | Page 102 of 156