AD9512-EP Datasheet, PDF (10/20 Pages) Analog Devices – 1.2 GHz Clock Distribution IC, 1.6 GHz Inputs, Dividers, Five Outputs

AD9512-EP
SERIAL CONTROL PORT
Table 6.
Parameter
CSB, SCLK (INPUTS)
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
SDIO (WHEN INPUT)
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
SDIO, SDO (OUTPUTS)
Output Logic 1 Voltage
Output Logic 0 Voltage
TIMING
Clock Rate (SCLK, 1/tSCLK)
Pulse Width High, tPWH
Pulse Width Low, tPWL
SDIO to SCLK Setup, tDS
SCLK to SDIO Hold, tDH
SCLK to Valid SDIO and SDO, tDV
CSB to SCLK Setup and Hold, tS, tH
CSB Minimum Pulse Width High, tPWH
Enhanced Product
Min
Typ
Max
Unit
Test Conditions/Comments
CSB and SCLK have 30 kΩ
internal pull-down resistors
2.0
V
0.8
V
110
µA
1
µA
2
pF
2.0
V
0.8
V
10
nA
10
nA
2
pF
2.7
V
0.4
V
25
MHz
16
ns
16
ns
2
ns
1
ns
6
ns
2
ns
3
ns
FUNCTION PIN
Table 7.
Parameter
INPUT CHARACTERISTICS
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Capacitance
RESET TIMING
Pulse Width Low
SYNC TIMING
Pulse Width Low
Min Typ Max Unit
2.0
V
0.8 V
110
µA
1
µA
2
pF
50
ns
1.5
High speed clock cycles
Test Conditions/Comments
The FUNCTION pin has a 30 kΩ internal pull-down resistor.
This pin should normally be held high. Do not let input float.
High speed clock is CLK1 or CLK2, whichever is being used
for distribution.
Rev. 0 | Page 10 of 20