AD9512-EP Datasheet, PDF (1/20 Pages) Analog Devices – 1.2 GHz Clock Distribution IC, 1.6 GHz Inputs, Dividers, Five Outputs

Enhanced Product
1.2 GHz Clock Distribution IC, 1.6 GHz Inputs,
Dividers, Five Outputs
AD9512-EP
FEATURES
Two 1.6 GHz, differential clock inputs
5 programmable dividers, 1 to 32, all integers
3 independent 1.2 GHz LVPECL outputs
Additive output jitter 225 fs rms
2 independent 800 MHz/250 MHz LVDS/CMOS clock outputs
Additive output jitter: 275 fs rms
Serial control port
Space-saving 48-lead LFCSP
ENHANCED PRODUCT FEATURES
Supports defense and aerospace applications (AQEC
standard)
Military temperature range (−55°C to +85°C)
Controlled manufacturing baseline
1 assembly/test site
1 fabrication site
Enhanced product change notification
Qualification data available on request
APPLICATIONS
Low jitter, low phase noise clock distribution
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
Defense and aerospace applications
FUNCTION
DSYNC
DSYNCB
CLK1
CLK1B
CLK2
CLK2B
SCLK
SDIO
SDO
CSB
FUNCTIONAL BLOCK DIAGRAM
VS GND RSET
SYNCB,
RESETB
PDB
DETECT
SYNC
SERIAL
CONTROL
PORT
VREF _AD9512-EP
PROGRAMMABLE
DIVIDERS AND
PHASE ADJUST
/1, /2, /3... /31, /32
SYNC
STATUS
LVPECL
/1, /2, /3... /31, /32
LVPECL
/1, /2, /3... /31, /32
LVPECL
/1, /2, /3... /31, /32
LVDS/CMOS
/1, /2, /3... /31, /32
LVDS/CMOS
SYNC
STATUS
OUT0
OUT0B
OUT1
OUT1B
OUT2
OUT2B
OUT3
OUT3B
OUT4
OUT4B
Figure 1.
GENERAL DESCRIPTION
The AD9512-EP provides a multi-output clock distribution
in a design that emphasizes low jitter and low phase noise to
maximize data converter performance. Other applications
with demanding phase noise and jitter requirements can also
benefit from this part.
There are five independent clock outputs. Three outputs are
LVPECL (1.2 GHz), and two are selectable as either LVDS
(800 MHz) or CMOS (250 MHz) levels.
Each output has a programmable divider that can be bypassed
or set to divide by any integer up to 32. The phase of one clock
output relative to another clock output can be varied by means
of a divider phase select function that serves as a coarse timing
adjustment.
The AD9512-EP is ideally suited for data converter clocking
applications where maximum converter performance is
achieved by encode signals with subpicosecond jitter.
The AD9512-EP is available in a 48-lead LFCSP and can be
operated from a single 3.3 V supply. The temperature range is
−55°C to +85°C.
Additional application and technical information can be found
in the AD9512 data sheet.
Note that the delay block element that exists in Channel 4 of the
AD9512 standard product is not supported in this AD9512-EP
version.
Rev. 0
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