AD8339 Datasheet, PDF (10/15 Pages) Analog Devices – Quad I/Q Demodulator And Phase Shifter

AD8339
Preliminary Technical Data
THEORY OF OPERATION
The AD8339 is a quad I/Q demodulator with a programmable
phase shifter for each channel. The primary application is
phased array beamforming in medical ultrasound. Other
potential applications might be phased array radar, and smart
antennas for mobile communications. The AD8339 can also be
used in applications that require multiple well-matched I/Q
demodulators. The AD8339 is architecturally very similar to its
predecessor – the AD8333. The major differences are:
1. the addition of a serial (SPI) interface that allows daisy-
chaining of multiple devices
2. reduced power per channel at the expense of a slight
decrease in dynamic range
Figure 1 shows the block diagram and pinout of the AD8339.
Four RF inputs accept signals from the RF sources, and a local
oscillator (applied to differential input pins marked 4LOP and 4
LON) common to all channels, comprise the analog inputs.
Each channel has the option to program 16 delay states/360° (or
22.5°/step) selectable via the SPI port. The part has two reset
inputs: RSET is used to synchronize the LO dividers in multiple
AD8339s used in arrays; RSTS is used to set the SPI port bits to
all zeros. This can be useful in testing or when one quickly
wants to turn off the device without first programming the SPI
port.
RF2N 1
RF2P 2
COMM 3
COMM 4
SCLK 5
CSB 6
VPOS 7
VPOS 8
RF3P 9
RF3N 10
BIAS
RSTS
SDI
SCLK
CSB
Serial
Interface
(SPI)
SDO
φ
I/V
V/I
CHANNEL 1
φ
I/V
φ
I/V
V/I
CHANNEL 2
φ
I/V
0
LO
Divide-by-4
90
φ
I/V
V/I
CHANNEL 3
φ
I/V
φ
I/V
V/I
CHANNEL 4
φ
I/V
30 Q2OP
29 I2OP
28 VPOS
27 VPOS
26 4LOP
25 4LON
24 VNEG
23 VNEG
22 I3OP
21 Q3OP
Figure 1. Block Diagram and Pinout
Each of the current formatted I and Q outputs sum together for
beamforming applications. Multiple channels are summed and
converted to a voltage using a transimpedance amplifier. If
desired, channels can also be used individually.
QUADRATURE GENERATION
The internal 0° and 90° LO phases are digitally generated by a
divide-by-four logic circuit. The divider is dc-coupled and
inherently broadband; the maximum LO frequency is limited
only by its switching speed. The duty cycle of the quadrature LO
signals is intrinsically 50% and is unaffected by the asymmetry
of the externally connected 4xLO input. Furthermore, the
divider is implemented such that the 4xLO signal re-clocks the
final flip-flops that generate the internal LO signals and thereby
minimizes noise introduced by the divide circuitry.
For optimum performance, the 4xLO input is driven
differentially, but can also be driven single-ended. A good
choice for a drive is an LVDS device. The common-mode range
on each pin is approximately 0.2 V to 3.8 V with the nominal ±5
V supplies.
The minimum 4xLO level is frequency dependent. For
optimum noise performance it is important to ensure that the
LO source has very low phase noise (jitter) and adequate input
level to assure stable mixer-core switching. The gain through
the divider determines the LO signal level vs. RF frequency. The
AD8339 can be operated to very low frequencies at the LO
inputs if a square wave is used to drive the LO.
Beamforming applications require a precise channel-to-channel
phase relationship for coherence among multiple channels. A
reset pin is provided to synchronize the LO divider circuits in
different AD8339s when they are used in arrays. The RSET pin
resets the dividers to a known state after power is applied to
multiple AD8339s. A logic input must be provided to the RSET
pin when using more than one AD8339. Note that at least one
channel must be enabled for the LO interface to also be enabled
and the LO reset to work. See the Reset Input section in the
applications section for more detail.
I/Q DEMODULATOR AND PHASE SHIFTER
The I/Q demodulators consist of double-balanced Gilbert cell
mixers. The RF input signals are converted into currents by
transconductance stages that have a maximum differential input
signal capability of 2.7 V p-p. These currents are then presented to
the mixers, which convert them to baseband: RF − LO and
RF + LO. The signals are phase shifted according to the codes
programmed into the SPI latch (see Table 4); the phase bits are
labeled PHx0 through PHx3 where ‘0’ indicates LSB and ‘3’
indicates MSB. The phase shift function is an integral part of the
overall circuit (patent pending). The phase shift listed in Column 1
of Table 4 is defined as being between the baseband I or Q channel
outputs. As an example, for a common signal applied to a pair of
RF-inputs to an AD8339, the baseband outputs are in phase for
matching phase codes. However, if the phase code for Channel 1 is
0000 and that of Channel 2 is 0001, then Channel 2 leads Channel 1
by 22.5°.
Following the phase shift circuitry, the differential current
signal is converted from differential to single-ended via a
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