AD8339 Datasheet, PDF (1/15 Pages) Analog Devices – Quad I/Q Demodulator And Phase Shifter

Quad I/Q Demodulator And Phase Shifter
Preliminary Technical Data
FEATURES
Quad Integrated I/Q Demodulator
16 Phase Select on each Output (22.5° per step)
Quadrature Demodulation Accuracy
Phase Accuracy ±1°
Amplitude Balance ±0.25 dB
Bandwidth
4LO: LF – 100 MHz; RF: LF - 25 MHz
Baseband: determined by external filtering
Output Dynamic Range 158 dB (1 Hz Bandwidth)
LO Drive > –10 dBm (50 Ω); 200 mVpp
Supply: ±5 V
Power Consumption 73 mW/channel (290 mW total)
Power Down via SPI (Each Channel and Complete Chip)
APPLICATIONS
Medical Imaging (CW Ultrasound Beamforming)
Phased Array Systems
Radar
Adaptive Antennas
Communication Receivers
GENERAL DESCRIPTION
The AD8339 is a Quad I/Q demodulator intended to be driven by a
low noise preamplifier with differential outputs; it is optimized for the
LNA in the AD8332/4/5 family of VGAs. The part consists of four
identical I/Q demodulators with a 4x local oscillator (LO) input that
divides this signal and generates the necessary 0° and 90° phases of
the internal LO that drive the mixers. The four I/Q demodulators can
be used independently of each other (assuming that a common LO is
acceptable) since each has a separate RF input.
The major application is continuous wave (CW) analog beamforming
in ultrasound. Since in a beamforming application the outputs of
many channels are summed coherently, the signals need to be phase
aligned. A reset pin for the LO divider that synchronizes multiple ICs
to start in the same quadrant is provided. Sixteen discrete phase
rotations in 22.5° increments can be selected independently for each
channel. For example, if CH1 is used as a reference and CH2 has an
I/Q phase lead of 45°, then by choosing the correct code one can
phase align CH2 with CH1.
The mixer outputs are provided in current form so that they can be
easily summed. The summed current outputs, one each for the I and
Rev. PrA - 12/19/06
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AD8339
FUNCTIONAL BLOCK DIAGRAM
RF1
2
0
BIAS
90
90
RSET
0
RF2
2
4xLO
/4
2
RF3
2
0
VPOS
90
COMM
90
VNEG
0
2
φ
φ
φ
φ
4
Serial
Interface
4
φ
φ
φ
φ
I1
Q1
Q2
I2
SCLK
SDI
SDO
CSB
I3
Q3
Q4
I4
RF4
Figure 1. Functional Block Diagram
Q signals, will need to be converted to a voltage by a high dynamic
range current-to-voltage (I-V) converter. A good choice for this
transimpedance amplifier is the AD8021 because of its low noise.
Following the current summation the combined signal is presented to
a high resolution AD converter (ADC) like the AD7665 (16b/570
ksps).
An SPI compatible serial interface is provided for ease of
programming the phase of each channel; the interface allows daisy-
chaining by shifting the data through each chip from SDI to SDO. The
SPI also allows for power down of each individual channel and the
complete chip. During power down the serial interface remains active
so that the device can be programmed again.
The dynamic range is >158 dB (1 Hz BW) at the I and Q outputs.
Note that the following transimpedance amplifier is an important
element in maintaining this dynamic range and attention needs to be
paid to component selection.
The AD8339 will be available in a 6x6 mm 40 pin LFCSP for the
industrial temperature range of -40°C to +85°C.
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