AD7765_07 Datasheet, PDF (10/32 Pages) Analog Devices – 24-Bit, 156 kSPS, 112 dB Σ-Δ ADC with On-Chip Buffers and Serial Interface

AD7765
Pin No.
14
15
16
19
18
Mnemonic
FSI
SYNC
RESET/
PWRDWN
MCLK
DEC_RATE
Description
Frame Sync Input. The status of this pin is checked on the falling edge of SCO. If this pin is low, then the first
data bit is latched in on the next SCO falling edge. See the AD7765 Interface section for further details.
Synchronization Input. A falling edge on this pin resets the internal filter. This can be used to synchronize
multiple devices in a system. See the Synchronization section for further details.
Reset/Powerdown Pin. When a logic low is sensed on this pin, the part is powered down and all internal
circuitry is reset.
Master Clock Input. A low jitter digital clock must be applied to this pin. The output data rate depends on the
frequency of this clock. See the Clocking the AD7765 section for more details.
Decimation Rate. This pin selects one of the three decimation rate modes. When 2.5 V is applied to this pin, a
decimation rate of 128× is selected. A decimation rate of 256× is selected by setting the pin to ground.
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