OP07Z Datasheet, PDF (1/16 Pages) Analog Devices – Ultralow Offset Voltage Operational Amplifier

Data Sheet
FEATURES
Low VOS: 75 μV maximum
Low VOS drift: 1.3 μV/°C maximum
Ultrastable vs. time: 1.5 μV per month maximum
Low noise: 0.6 μV p-p maximum
Wide input voltage range: ±14 V typical
Wide supply voltage range: ±3 V to ±18 V
125°C temperature-tested dice
APPLICATIONS
Wireless base station control circuits
Optical network control circuits
Instrumentation
Sensors and controls
Thermocouples
Resistor thermal detectors (RTDs)
Strain bridges
Shunt current measurements
Precision filters
GENERAL DESCRIPTION
The OP07 has very low input offset voltage (75 μV maximum for
OP07E) that is obtained by trimming at the wafer stage. These
low offset voltages generally eliminate any need for external
nulling. The OP07 also features low input bias current (±4 nA for
the OP07E) and high open-loop gain (200 V/mV for the OP07E).
The low offset and high open-loop gain make the OP07
particularly useful for high gain instrumentation applications.
Ultralow Offset Voltage
Operational Amplifier
OP07
PIN CONFIGURATION
V_OS TRIM 1
–IN 2
+IN 3
V– 4
OP07
8 V_OS TRIM
7 V+
6 OUT
5 NC
NC = NO CONNECT
Figure 1.
The wide input voltage range of ±13 V minimum combined
with a high CMRR of 106 dB (OP07E) and high input
impedance provide high accuracy in the noninverting circuit
configuration. Excellent linearity and gain accuracy can be
maintained even at high closed-loop gains. Stability of offsets
and gain with time or variations in temperature is excellent. The
accuracy and stability of the OP07, even at high gain, combined
with the freedom from external nulling have made the OP07 an
industry standard for instrumentation applications.
The OP07 is available in two standard performance grades. The
OP07E is specified for operation over the 0°C to 70°C range,
and the OP07C is specified over the −40°C to +85°C
temperature range.
The OP07 is available in epoxy 8-lead PDIP and 8-lead narrow
SOIC packages. For CERDIP and TO-99 packages and standard
microcircuit drawing (SMD) versions, see the OP77.
V+
7
R2A¹
R2B¹
R1A
(OPTIONAL
1 ^NULL) 8
R1B
C1
Q9
Q10
Q7
Q8
Q11 Q12
Q5
Q3 Q6
Q4
NONINVERTING ^R3
Q27 ^C3
C2
Q17
INPUT ₃
Q1
R5
Q21
Q23
Q26
INVERTING ^R4
Q22
Q24
INPUT ₂
Q2
Q25
Q14
Q13
4
V–
1_{R2A AND R2B ARE ELECTRONICALLY ADJUSTED ON CHIP AT FACTORY FOR MINIMUM INPUT OFFSET VOLTAGE.}
Figure 2. Simplified Schematic
R7
Q19
Q16
Q15
Q18
R9
OUT
6
R10
Q20
R6 R8
Rev. G
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