ADUCM322I Datasheet, PDF (1/23 Pages) Analog Devices – general-purpose timers

Data Sheet
Precision Analog Microcontroller, Analog I/O
with MDIO Interface, ARM Cortex-M3
ADuCM322i
FEATURES
Analog input/output
Multichannel, 12-bit, 1 MSPS analog-to-digital
converter (ADC)
Up to 16 ADC input channels
0 V to VREF analog input range
Single-ended mode
AVDD and IOVDD monitors
12-bit voltage output digital-to-analog converters (VDACs)
8 VDACs with a range of 0 V to 2.5 V or AVDD outputs
Voltage comparator
Microcontroller
ARM Cortex-M3 processor, 32-bit RISC architecture
Serial wire port supports code download and debug
Clocking options
80 MHz phase-locked loop (PLL) with programmable divider
Trimmed on-chip oscillator (±3%)
External 16 MHz crystal option
External clock source up to 80 MHz
Memory
2 × 128 kB independent Flash/EE memories
10,000 cycle Flash/EE endurance
20-year Flash/EE retention
32 kB SRAM
Software triggered in-circuit reprogrammability via I²C
On-chip peripherals
MDIO slave up to 4 MHz
2 × I²C, 2 × SPI, UART
Multiple general-purpose input/output (GPIO) balls: 3.6 V
compliant
7 × 1.2 V compatible when used for MDIO
32-element programmable logic array (PLA)
3 general-purpose timers
Wake-up timer
Watchdog timer
16-bit pulse width modulator (PWM)
Power
Supply range: 2.9 V to 3.6 V
Flexible operating modes for low power applications
Packages and temperature range
6 mm × 6 mm, 96-ball CSP_BGA package
Fully specified for −40°C to +105°C ambient operation
Tools
QuickStart development system
Full third-party support
APPLICATIONS
Optical networking
AIN0
AIN5
AIN6
AIN15
VDAC0
VDAC7
FUNCTIONAL BLOCK DIAGRAM
BUF_VREF2V5
XTALO XTALI ECLKIN
2.5V BAND GAP
1.8 V LDO
MUX
SAR ADC
CLOCK SYSTEM
32.768kHz
16MHz OSC
80MHz PLL
DGNDx
AVDDx
AGNDx
IOVDDx
IOGNDx
INTERNAL
CHANNELS:
TEMPERATURE,
AV_DD, IOV_DD
COMPARATOR
VDAC
VDAC
ADuCM322i
ARM
CORTEX-M3
PROCESSOR
MEMORY
2 × 128kB FLASH
32kB SRAM
DMA
NVIC
RESET SYSTEM
GPIO PORTS
UART
2 × SPI
2 × I²C
EXT IRQS
MDIO
PLA
3 × GP TIMER
WD TIMER
WAKE-UP TIMER
PWM
SERIAL WIRE
GENERAL
PURPOSE
I/O PORTS
PWM0 TO
PWM6
SWDIO
SWCLK
RESET
Figure 1.
Rev. 0
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