ADSP-TS201S Datasheet, PDF (1/40 Pages) Analog Devices – TigerSHARC-R Embedded Processor

Preliminary Technical Data
KEY FEATURES
Up to 600 MHz, 1.67 ns Instruction Cycle Rate
24M Bits of Internal—On-Chip—DRAM Memory
25×25 mm (576-Ball) Thermally Enhanced Ball Grid Array
Package
Dual Computation Blocks—Each Containing an ALU, a Multi-
plier, a Shifter, a Register File, and a Communications Logic
Unit (CLU)
Dual Integer ALUs, providing Data Addressing and Pointer
Manipulation
Integrated I/O Includes 14 Channel DMA Controller, External
Port, Four Link Ports, SDRAM Controller, Programmable
Flag Pins, Two Timers, and Timer Expired Pin for System
Integration
1149.1 IEEE Compliant JTAG Test Access Port for On-Chip
Emulation
On-Chip Arbitration for Glueless Multiprocessing
TigerSHARC^®
Embedded Processor
ADSP-TS201S
KEY BENEFITS
Provides High-Performance Static Superscalar DSP Opera-
tions, Optimized for Telecommunications Infrastructure
and Other Large, Demanding Multiprocessor DSP
Applications
Performs Exceptionally Well on DSP Algorithm and I/O
Benchmarks (See Benchmarks in Table 1)
Supports Low-Overhead DMA Transfers Between Internal
Memory, External Memory, Memory-Mapped Peripherals,
Link Ports, Host Processors, and Other (Multiprocessor)
DSPs
Eases DSP Programming Through Extremely Flexible Instruc-
tion Set and High-Level-Language Friendly DSP
Architecture
Enables Scalable Multiprocessing Systems With Low Commu-
nications Overhead
DATA ADDRESS GENERATION
INTEGER ³²
J ALU
32 _INTEGER
K ALU
PROGRAM
SEQUENCER
ADDR
FETCH
32X32
J-BUS ADDR
J-BUS DATA
32X32
BTB
K-BUS ADDR
K-BUS DATA
I-BUS ADDR
PC
I-BUS DATA
IAB
T
24M BITS INTERNAL MEMORY
MEMORY BLOCKS
(PAGE CACHE)
4xCROSSBAR CONNECT
32 ^{A D A D A D A D}
128
32
128
32
128
S-BUS ADDR
32
S-BUS DATA 128
128
X
REGISTER ₁₂₈
FILE
32x32
DAB
DAB
128
Y
128 ^REGISTER
FILE
32x32
COMPUTATIONAL BLOCKS
SOC BUS
JTAG PORT
6
JTAG
EXTERNAL
PORT
HOST
32
ADDR
MULTI
PROC
64
DATA
SDRAM
CTRL
8
CTRL
C-BUS ¹⁰ _CTRL
ARB
EXT DMA
REQ 4
DMA
LINK PORTS
4
IN 8
L0
4
OUT 8
4
IN 8
L1
4
OUT 8
4
IN 8
L2
4
OUT 8
4
IN 8
L3
4
OUT 8
Figure 1. Functional block diagram
TigerSHARC and the TigerSHARC logo are registered trademarks of Analog Devices, Inc.
Rev. PrH
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