ADSP-BF547_15 Datasheet, PDF (1/102 Pages) Analog Devices – Blackfin Embedded Processor

Blackfin
Embedded Processor
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
FEATURES
Up to 600 MHz high performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs
RISC-like register and instruction model
Wide range of operating voltages and flexible booting
options
Programmable on-chip voltage regulator
400-ball CSP_BGA, RoHS compliant package
MEMORY
Up to 324K bytes of on-chip memory comprised of
instruction SRAM/cache; dedicated instruction SRAM; data
SRAM/cache; dedicated data SRAM; scratchpad SRAM
External sync memory controller supporting either DDR
SDRAM or mobile DDR SDRAM
External async memory controller supporting 8-/16-bit async
memories and burst flash devices
NAND flash controller
4 memory-to-memory DMA pairs, 2 with ext. requests
Memory management unit providing memory protection
Code security with Lockbox secure technology and 128-bit
AES/ARC4 data encryption
One-time-programmable (OTP) memory
PERIPHERALS
High speed USB On-the-Go (OTG) with integrated PHY
SD/SDIO controller
ATA/ATAPI-6 controller
Up to 4 synchronous serial ports (SPORTs)
Up to 3 serial peripheral interfaces (SPI-compatible)
Up to 4 UARTs, two with automatic H/W flow control
Up to 2 CAN (controller area network) 2.0B interfaces
Up to 2 TWI (2-wire interface) controllers
8- or 16-bit asynchronous host DMA interface
Multiple enhanced parallel peripheral interfaces (EPPIs),
supporting ITU-R BT.656 video formats and 18-/24-bit LCD
connections
Media transceiver (MXVR) for connection to a MOST network
Pixel compositor for overlays, alpha blending, and color
conversion
Up to eleven 32-bit timers/counters with PWM support
Real-time clock (RTC) and watchdog timer
Up/down counter with support for rotary encoder
Up to 152 general-purpose I/O (GPIOs)
On-chip PLL capable of frequency multiplication
Debug/JTAG interface
CAN (0-1)
TWI (0-1)
TIMERS(0-10)
COUNTER
KEYPAD
PAB 16
VOLTAGE
REGULATOR
JTAG TEST AND
EMULATION
RTC
B
WATCHDOG
TIMER
OTP
INTERRUPTS
L2
SRAM
L1
INSTR ROM
L1
INSTR SRAM
L1
DATA SRAM
MXVR
USB
DCB 32
EAB 64
DEB 32
BOOT
ROM
EXTERNAL PORT
NOR, DDR, MDDR
DDR/MDDR
16
ASYNC
16
32-BIT DMA
16-BIT DMA
DAB1 32
DAB0 16
ATAPI
NAND FLASH
CONTROLLER
Figure 1. ADSP-BF549 Functional Block Diagram
HOST DMA
UART (0-1)
UART (2-3)
SPI (0-1)
SPI (2)
SPORT (2-3)
SPORT (0-1)
SD / SDIO
EPPI (0-2)
PIXEL
COMPOSITOR
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. E
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