ADAU1777 Datasheet, PDF (1/108 Pages) Analog Devices – Four-ADC, Two-DAC, Low Power Codec with Audio Processor

Data Sheet
Four-ADC, Two-DAC, Low Power Codec
with Audio Processor
ADAU1777
FEATURES
APPLICATIONS
Programmable audio processing engine
Fast (up to 768 kHz) and slow processing paths
Biquad filters, limiters, volume controls, and mixing
Low latency, 24-bit ADCs and DACs
102 dB SNR (through PGA and ADC with A weighted filter)
108 dB combined SNR (through DAC and headphone with
A weighted filter)
Serial port sampling rate from 8 kHz to 192 kHz
5 μs analog-to-analog latency
4 single-ended analog inputs, configurable as microphone
or line inputs
Dual stereo digital microphone inputs
Stereo analog audio output, single-ended or differential,
configurable as either line output or headphone driver
PLL supporting any input clock rate from 8 MHz to 27 MHz
Full duplex, asynchronous sample rate converters (ASRCs)
Power supplies
Analog and digital input/output of 1.8 V to 3.3 V
Digital signal processing (DSP) core of 1.1 V to 1.8 V
Low power
I²C and SPI control interfaces, self boot from I²C EEPROM
7 multipurpose (MPx) pins for digital controls and outputs
Noise canceling handsets, headsets, and headphones
Bluetooth® active noise canceling (ANC) handsets, headsets,
and headphones
Personal navigation devices
Digital still and video cameras
GENERAL DESCRIPTION
The ADAU1777 is a codec with four inputs and two outputs that
incorporates a digital processing engine to perform filtering,
level control, signal level monitoring, and mixing. The path
from the analog input to the DSP core to the analog output is
optimized for low latency and is ideal for noise canceling headsets.
With the addition of just a few passive components, a crystal,
and an EEPROM for booting, the ADAU1777 provides a complete
headset solution.
Note that throughout this data sheet, multifunction pins, such as
SCL/SCLK, are referred to either by the entire pin name or by a
single function of the pin, for example, SCLK, when only that
function is relevant.
FUNCTIONAL BLOCK DIAGRAM
MICBIAS0
MICBIAS1
AIN0
AIN1
DMIC0_1/MP4
DMIC2_3/MP5
AIN2
AIN3
CM
MICROPHONE
BIAS GENERATORS
PGA
ADC
PGA
ADC
DIGITAL
MICROPHONE
INPUTS
PGA
ADC
PGA
ADC
POWER
MANAGEMENT
LDO
REGULATOR
ADAU1777
PLL
CLOCK
OSCILLATOR
INPUT/OUTPUT
SIGNAL
ROUTING
DSP CORE:
BIQUAD FILTERS,
LIMITERS,
VOLUME CONTROLS,
MIXING
DAC
STEREO PDM
MODULATOR
DAC
BIDIRECTIONAL
ASRCS
SERIAL
INPUT/
OUTPUT
PORT
I²C/SPI CONTROL
INTERFACE AND SELF BOOT
ADC_SDATA1/CLKOUT/MP6
XTALI/MCLKIN
XTALO
HPOUTLP/LOUTLP
HPOUTLN/LOUTLN
HPOUTRP/LOUTRP
HPOUTRN/LOUTRN
DAC_SDATA/MP0
ADC_SDATA0/PDMOUT/MP1
BCLK/MP2
LRCLK/MP3
Figure 1.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
©2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com